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?otorola, inc., 1996 how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036. 1-800-441-2447 or 602/303-5454 mfax: rmfax0@email.sps.mot.com - touchtone (602) 244-6609 internet: http://design-net.com japan: nippon motorola ltd.; tatsumi-spd-jldc, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 81-3-3521-8315 asia pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298 motorola reserves the right to make changes without further notice to any products herein. motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "typical" parameters which may be provided in motorola data sheets and/or specifications can and do vary in different applications. all operating parameters, including "typicals" must be validated for each customer application by customer's technical experts. motorola does not convey any license under its patent rights nor the rights of others. motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the motorola product could create a situation where personal injury or death may occur. should buyer purchase or use motorola products for any such unintended or unauthorized application, buyer shall indemnify and hold motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola was negligent regarding the design or manufacture of the part. mcuinit, mcuasm, mcudebug, and rtek are trademarks of motorola, inc. motorola and the motorola logo are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/affirmative action employer. MC68HC58 data link controller

MC68HC58 motorola technical data iii paragraph title page section 1introduction section 2signal and pin descriptions 2.1 MC68HC58 dlc parallel mode ................................................................ 2-1 2.1.1 dlc parallel mode pin function ....................................................... 2-2 2.1.1.1 addr0 ?address bit .............................................................. 2-2 2.1.1.2 bus ?sae j1850 multiplex bus ............................................. 2-2 2.1.1.3 cs ?dlc chip-select ............................................................. 2-2 2.1.1.4 data[7:0] ?dlc data bus ..................................................... 2-3 2.1.1.5 eclk ?6800 bus clock .......................................................... 2-3 2.1.1.6 int ?dlc interrupt request ................................................... 2-3 2.1.1.7 lito ?logic in transceiver out ............................................. 2-3 2.1.1.8 load ?external bus load ..................................................... 2-3 2.1.1.9 loti ?logic out transceiver in ............................................. 2-3 2.1.1.10 osc1, osc2 ?external oscillator .......................................... 2-3 2.1.1.11 prlmd ?parallel mode .......................................................... 2-3 2.1.1.12 psen ?power supply enable ................................................ 2-3 2.1.1.13 rst ?dlc reset .................................................................... 2-4 2.1.1.14 rext ?external bias resistor ................................................ 2-4 2.1.1.15 r/w ?read/write strobe ........................................................ 2-4 2.1.1.16 v batt ?battery voltage .......................................................... 2-4 2.1.1.17 v cc ?analog power supply voltage ...................................... 2-4 2.1.1.18 vdd ?digital power supply voltage ....................................... 2-4 2.1.1.19 vssa ?analog power ground ................................................ 2-4 2.1.1.20 vssd ?digital power ground ................................................. 2-4 2.1.2 example dlc parallel mode system ................................................ 2-5 2.2 MC68HC58 dlc serial mode ................................................................... 2-7 2.2.1 dlc serial mode pin function .......................................................... 2-7 2.2.1.1 bus ?sae j1850 multiplex bus ............................................. 2-7 2.2.1.2 cs ?dlc chip-select ............................................................. 2-7 2.2.1.3 int ?dlc interrupt request ................................................... 2-8 2.2.1.4 lito ?logic in transceiver out ............................................. 2-8 2.2.1.5 load ?external bus load ..................................................... 2-8 2.2.1.6 loti ?logic out transceiver in ............................................. 2-8 2.2.1.7 osc1, osc2 ?external oscillator .......................................... 2-8 2.2.1.8 prlmd ?arallel mode ........................................................... 2-8 2.2.1.9 psen ?power supply enable ................................................ 2-8 2.2.1.10 rst ?dlc reset .................................................................... 2-8 2.2.1.11 rext ?external bias resistor ................................................ 2-8 2.2.1.12 sclk ?serial clock ................................................................ 2-9 2.2.1.13 simo ?slave in master out .................................................... 2-9 table of contents
motorola MC68HC58 iv technical data (continued) paragraph title page table of contents 2.2.1.14 somi ?slave out master in .................................................... 2-9 2.2.1.15 vbatt ?battery voltage ........................................................ 2-9 2.2.1.16 vcc ?analog power supply voltage ..................................... 2-9 2.2.1.17 vdd ?digital power supply voltage ....................................... 2-9 2.2.1.18 vssa ?analog power ground ................................................ 2-9 2.2.1.19 vssd ?digital power ground ................................................. 2-9 2.2.2 example dlc serial mode system ................................................. 2-10 2.3 bus loading ............................................................................................ 2-12 2.4 dlc clock sources ................................................................................. 2-12 2.4.1 logic clock ...................................................................................... 2-12 2.4.2 host interface clock ........................................................................ 2-12 2.5 power supply connections ..................................................................... 2-13 2.5.1 method 1 ?all supplies applied .................................................... 2-14 2.5.2 method 2 ?switching vdd with psen ......................................... 2-15 2.5.3 method 3 ?switching vdd and vcc simultaneously ................... 2-16 2.6 reset ....................................................................................................... 2-17 section 3 j1850 frame format 3.1 j1850 frame format ................................................................................. 3-1 3.1.1 sof ?start of frame symbol ......................................................... 3-2 3.1.2 data ?in frame data bytes ............................................................ 3-2 3.1.2.1 logic zero ................................................................................. 3-3 3.1.2.2 logic one .................................................................................. 3-3 3.1.3 crc ?cyclical redundancy check byte ........................................ 3-3 3.1.4 eod ?end of data symbol ............................................................. 3-3 3.1.5 nb ?normalization bit ..................................................................... 3-3 3.1.6 ifr ?in-frame response bytes ..................................................... 3-4 3.1.7 eof ?end of frame symbol ........................................................... 3-4 3.1.8 ifs ?inter-frame separation symbol ............................................. 3-4 3.1.9 break ?break ............................................................................... 3-4 3.1.10 idle bus ............................................................................................. 3-5 3.2 j1850 vpw valid/invalid bits and symbols .............................................. 3-5 3.2.1 invalid passive bit ............................................................................. 3-7 3.2.2 valid passive logic zero ................................................................... 3-7 3.2.3 valid passive logic one ................................................................... 3-7 3.2.4 valid eod symbol ............................................................................. 3-7 3.2.5 valid eof and ifs symbol ............................................................... 3-7 3.2.6 idle bus ............................................................................................. 3-7 3.2.7 invalid active bit ................................................................................ 3-7 3.2.8 valid active logic one ...................................................................... 3-8 3.2.9 valid active logic zero ...................................................................... 3-8
MC68HC58 motorola technical data v (continued) paragraph title page table of contents 3.2.10 valid sof symbol ............................................................................. 3-9 3.2.11 valid break symbol ........................................................................ 3-9 3.3 frame arbitration ....................................................................................... 3-9 section 4 data link controller operation 4.1 operating modes ....................................................................................... 4-1 4.1.1 power-off mode ................................................................................ 4-2 4.1.2 reset mode ....................................................................................... 4-2 4.1.3 normal mode ..................................................................................... 4-2 4.1.4 standby mode ................................................................................... 4-2 4.1.5 4x mode ............................................................................................ 4-2 4.1.6 block mode ........................................................................................ 4-3 4.2 host interface ............................................................................................ 4-3 4.2.1 MC68HC58 dlc parallel mode host mcu interface ........................ 4-5 4.2.1.1 parallel mode data transfer ..................................................... 4-5 4.2.1.2 servicing sequence .................................................................. 4-6 4.2.1.3 minimum time requirements ................................................... 4-7 4.2.1.4 motorola microcontroller data transfers ................................... 4-7 4.2.2 MC68HC58 dlc serial mode host mcu interface ........................... 4-8 4.2.2.1 serial mode data transfer ........................................................ 4-8 4.2.2.2 servicing sequence .................................................................. 4-9 4.2.2.3 spi exchange ........................................................................... 4-9 4.2.2.4 initialization ............................................................................. 4-10 4.2.3 interrupt requests ........................................................................... 4-11 4.3 transmitter operation ............................................................................. 4-12 4.4 receiver operation ................................................................................. 4-16 4.5 block mode operation ............................................................................. 4-20 4.6 break operation ................................................................................... 4-21 4.7 in-frame response (ifr) ....................................................................... 4-21 section 5 control and status codes 5.1 command byte .......................................................................................... 5-1 5.1.1 gcom[7:5] ?general command field ........................................... 5-1 5.1.1.1 do nothing ................................................................................ 5-2 5.1.1.2 enter standby mode ................................................................. 5-2 5.1.1.3 send break symbol ................................................................ 5-2 5.1.1.4 send ifr on eod with crc ..................................................... 5-2 5.1.1.5 terminate auto retry ................................................................ 5-3 5.1.1.6 send ifr on eod without crc ................................................ 5-3 5.1.1.7 abort transmission ................................................................... 5-4
motorola MC68HC58 vi technical data (continued) paragraph title page table of contents 5.1.2 btad[4:2] ?byte type and destination field ................................. 5-4 5.1.2.1 do not load .............................................................................. 5-4 5.1.2.2 load as transmit data .............................................................. 5-4 5.1.2.3 load as last byte of transmit data .......................................... 5-5 5.1.2.4 load as configuration byte ....................................................... 5-5 5.1.2.5 load as first byte of transmit data .......................................... 5-5 5.1.2.6 load as configuration byte ?immediate .................................. 5-5 5.1.2.7 load as first and last byte of frame ....................................... 5-6 5.1.3 rfc[1:0] ?receive fifo command field ...................................... 5-6 5.1.3.1 do nothing ................................................................................ 5-6 5.1.3.2 flush byte ................................................................................. 5-6 5.1.3.3 flush frame .............................................................................. 5-6 5.2 configuration byte ..................................................................................... 5-7 5.2.1 tm ?test mode control bit ............................................................. 5-7 5.2.2 tc[6:5] ?test configuration field ................................................... 5-7 5.2.3 imsk ?interrupt mask bit ................................................................ 5-7 5.2.4 imod ?interrupt mode bit ............................................................... 5-8 5.2.5 oscd[2:1] ?oscillator divisor field ................................................ 5-8 5.2.6 4x ?high-speed control bit ............................................................ 5-8 5.3 status byte ................................................................................................ 5-8 5.3.1 rfs[7:5] ?receive fifo status field ............................................ 5-9 5.3.1.1 buffer invalid or empty .............................................................. 5-9 5.3.1.2 buffer contains more than one byte ....................................... 5-9 5.3.1.3 buffer contains a completion code .......................................... 5-9 5.3.1.4 thirteenth byte received .......................................................... 5-9 5.3.1.5 one byte in buffer ................................................................... 5-10 5.3.1.6 completion code at head of buffer, more bytes available .... 5-10 5.3.1.7 completion code at head of buffer, frame available ............ 5-10 5.3.1.8 completion code only at head of buffer ................................ 5-10 5.3.2 dli ?data link idle bit .................................................................. 5-10 5.3.3 netf ?network fault bit .............................................................. 5-10 5.3.4 4xmd ?4x mode bit ..................................................................... 5-11 5.3.5 tmfs[1:0] ?txfifo status field .................................................. 5-11 5.3.5.1 buffer empty ........................................................................... 5-11 5.3.5.2 buffer contains data ............................................................... 5-11 5.3.5.3 buffer almost full .................................................................... 5-11 5.3.5.4 buffer full ................................................................................ 5-11 5.4 completion code byte ............................................................................ 5-11 5.4.1 errf ?error bit ............................................................................ 5-12 5.4.2 rfo ?receive fifo overrun bit .................................................. 5-12 5.4.3 tms[5:4] ?transmitter status field .............................................. 5-12
MC68HC58 motorola technical data vii (continued) paragraph title page table of contents 5.4.3.1 transmitter not involved ......................................................... 5-12 5.4.3.2 transmitter underrun .............................................................. 5-12 5.4.3.3 transmitter lost arbitration ..................................................... 5-13 5.4.3.4 transmitter successful ............................................................ 5-13 5.4.4 ifr ?in-frame response bit ........................................................ 5-13 5.4.5 ifrc ?in-frame response crc bit ............................................. 5-13 5.4.6 errc[1:0] ?error code field ....................................................... 5-13 5.4.6.1 crc error ............................................................................... 5-13 5.4.6.2 incomplete byte error ............................................................. 5-13 5.4.6.3 bit timing error ....................................................................... 5-14 5.4.6.4 break error ........................................................................... 5-14 appendix a electrical characteristics appendix b mechanical data and ordering information b.1 pin assignments ....................................................................................... b-1 5.5 package dimensions ................................................................................ b-3 b.2 obtaining updated MC68HC58 mechanical information ......................... b-4 b.3 ordering information ................................................................................ b-4 appendix c dlc registers c.1 command byte register .......................................................................... c-1 c.2 configuration byte register ..................................................................... c-2 c.3 status byte register ................................................................................. c-3 c.4 completion code byte register ............................................................... c-4
motorola MC68HC58 viii technical data (continued) paragraph title page table of contents
MC68HC58 motorola technical data ix figure title page 1-1 MC68HC58 dlc parallel mode block diagram ............................................. 1-3 1-2 MC68HC58 dlc serial mode block diagram ................................................ 1-4 2-1 MC68HC58 dlc pin assignments ................................................................. 2-1 2-2 dlc parallel mode circuit .............................................................................. 2-5 2-3 dlc serial mode circuit ............................................................................... 2-10 2-4 method 1 ?standby mode supplies applied .............................................. 2-14 2-5 method 2 ?switching vdd with psen ....................................................... 2-15 2-6 method 3 ?switching vdd and vcc in standby mode ............................. 2-16 3-1 j1850 bus message components ................................................................. 3-1 3-2 j1850 bus frame format (vpw) ................................................................... 3-1 3-3 j1850 vpw symbols ...................................................................................... 3-5 3-4 j1850 vpw passive symbols ........................................................................ 3-6 3-5 j1850 vpw active symbols ........................................................................... 3-8 3-6 j1850 vpw bitwise arbitration ....................................................................... 3-9 4-1 dlc operating modes .................................................................................... 4-1 4-2 dlc usage ..................................................................................................... 4-3 4-3 dlc operation ............................................................................................... 4-5 4-4 parallel mode byte format ............................................................................. 4-6 4-5 dlc serial mode byte format ....................................................................... 4-8 4-6 spi transfer ?clock polarity low .............................................................. 4-10 4-7 spi transfer ?clock polarity high ............................................................. 4-10 4-8 host/dlc serial mode initialization routine ................................................ 4-11 4-9 host/dlc serial mode transmit routine (part 1 of 2) ................................. 4-14 4-10 host/dlc serial mode transmit routine (part 2 of 2) ................................. 4-15 4-11 host/dlc serial mode receive routine (part 1 of 2) .................................. 4-18 4-12 host/dlc serial mode receive routine (part 2 of 2) .................................. 4-19 a-1 parallel interface timing ................................................................................. a-3 a-2 spi timing ?active high sclk .................................................................... a-5 a-3 spi timing ?active low sclk .................................................................... a-5 a-4 dlc interrupt timing ...................................................................................... a-7 a-5 reset timing .................................................................................................. a-8 a-6 variable pulse-width modulation (vpw) symbol timings ............................. a-9 b-1 MC68HC58 28-pin plcc ............................................................................... b-1 b-2 MC68HC58 28-pin soic ............................................................................... b-2 b-3 case outline #776-02 .................................................................................... b-3 b-4 case outline #751f-04 .................................................................................. b-4 list of illustrations
motorola MC68HC58 x technical data (continued) figure title page list of illustrations
MC68HC58 motorola technical data xi table title page 2-1 MC68HC58 dlc parallel mode pin function........................................................ 2-2 2-2 MC68HC58 dlc serial mode pin functions......................................................... 2-7 4-1 parallel transfers................................................................................................... 4-6 4-2 minimum time between operations...................................................................... 4-7 4-3 serial transfers ..................................................................................................... 4-9 4-4 ifr error conditions ............................................................................................ 4-22 5-1 general command summary ................................................................................ 5-2 5-2 byte type and destination summary .................................................................... 5-4 5-3 rfc field encoding............................................................................................... 5-6 5-4 internal clock frequency derivations................................................................... 5-8 5-5 rfs field encoding.............................................................................................. 5-9 5-6 tmfs field encoding .......................................................................................... 5-11 5-7 tms field encoding ............................................................................................ 5-12 5-8 errc field encoding......................................................................................... 5-13 a-1 operating conditions............................................................................................. a-1 a-2 electrical characteristics ....................................................................................... a-2 a-3 absolute maximum ratings................................................................................... a-2 a-4 parallel interface parameters................................................................................ a-4 a-5 serial interface parameters................................................................................... a-6 a-6 standby and interrupt timing ................................................................................ a-8 a-7 reset timing ......................................................................................................... a-9 a-8 transceiver requirements (dc).......................................................................... a-10 a-9 transmitter vpw symbol timings ...................................................................... a-10 a-10 receiver vpw symbol timings ........................................................................ a-10 b-1 MC68HC58 ordering information.......................................................................... b-4 c-1 general command summary (gcom).................................................................c-1 c-2 byte type and destination summary (btad).......................................................c-1 c-3 rfc field encoding (rfc) ...................................................................................c-1 c-4 test mode control bit (tm)...................................................................................c-2 c-5 test configuration field (tc)................................................................................c-2 c-6 interrupt mask bit (imsk)......................................................................................c-2 c-7 interrupt mode bit (imod).....................................................................................c-2 c-8 internal clock frequency field (oscd)................................................................c-2 c-9 high-speed control bit (4x)..................................................................................c-2 c-10 receive fifo status field encoding (rfs) .......................................................c-3 c-11 data link idle bit (dli) ........................................................................................c-3 c-12 network fault bit (netf) ....................................................................................c-3 c-13 4x mode bit (4xmd) ...........................................................................................c-3 c-14 transmit fifo status field encoding (tmfs)....................................................c-3 c-15 error bit (errf)..................................................................................................c-4 c-16 receive fifo overrun bit (rfo)........................................................................c-4 list of tables
motorola MC68HC58 xii technical data (continued) table title page list of tables c-17 transmitter status field encoding (tms) ...........................................................c-4 c-18 in-frame response bit (ifr) ..............................................................................c-4 c-19 in-frame response crc bit (ifrc)...................................................................c-4 c-20 error code field encoding..................................................................................c-4
MC68HC58 introduction motorola technical data 1-1 section 1introduction the MC68HC58 dlc (data link controller) handles microcontroller unit (mcu) to society of automotive engineers (sae) j1850 bus interface duties. the MC68HC58 dlc is the successor to the mc68hc56 dlcp (data link controller parallel) and the mc68hc57 dlcs (data link controller serial). the MC68HC58 is pin configurable to communicate with a host mcu via an 8-bit non-multiplexed parallel data bus or a motorola serial peripheral interface. the dlc consists of control logic and bus transceiver circuits. figure 1-1 shows the internal structure of a dlc configured for parallel mode. figure 1-2 shows the internal structure of a dlc configured for serial mode. the built-in bus transceiver allows the dlc to be directly connected to the j1850 bus, thus providing a complete link between the central processing unit (cpu) host application and the j1850 bus. the j1850 bus protocol is a method of information transfer via messages (frames) between nodes. a node is any location on the j1850 bus that sends and receives messages. the following are primary features of the dlc: ?sae j1850 compatible ?class 2 (vehicle bus communication protocol) compatible ?handles all network protocol functions (access, arbitration, error detection) ?supports polled or interrupt host dlc servicing ?message buffering on transmit and receive ?on-board transceiver with waveshaping ?operates with up to a 2-volt ground offset between network nodes ?pin configurable spi or parallel host interface ?digitally filtered receiver ?host configurable oscillator divisor ?power conserving sleep feature with fast wakeup on bus or host activity ?high voltage cmos (40 volt hvcmos) process ?built-in transient and esd protection the dlc handles sae j1850 frames with minimal mcu servicing. each dlc can be operated in either interrupt mode or polled mode. internal first in/first out (fifo) buffers, 20 bytes for receiver data and 11 bytes for transmitter data, allow full frame length operations. the mcu typically transfers complete frames to the dlc for transmission on the sae j1850 bus, and is interrupted only when a complete frame is received from the sae j1850 bus. the dlc handles all arbitration, error detection, and optional in-frame response duties internally. changes to the operating configuration can be made at any time. depending upon the command, the changes can be made immediately or following the current j1850 bus transaction.
motorola introduction MC68HC58 1-2 technical data the logic section of the dlc consists of the mcu interface, transmit and receive bit timing logic, transmit and receive fifo buffer logic, the control and timing block (fram- ing, error detection and bus arbitration), and command and status control logic. the bus transceiver allows the dlc to be directly connected to the j1850 bus, thus providing a complete link between the mcu application and the j1850 bus. transceiver operation is constrained by available power and the need to function reli- ably in the presence of conducted and induced noise. the main source of conducted noise is the ground offset between nodes. the dlc operates correctly under any com- bination of offsets up to a maximum differential of two volts at any frequency. induced noise tends to be composed of short-duration pulses. the receive bit timing section includes a digital filter to remove these pulses. the transceiver provides a waveshaped seven volt serial analog signal in response to a timed signal from the bit timing logic. the transceiver also receives j1850 bus wave- forms, and provides the control logic with unfiltered inputs. to achieve the 7-volt signal level necessary for the j1850 bus, the transceiver has a separate 9- to 16-volt power supply input (v batt ) . the transceiver actively drives the j1850 bus high, and passively allows an rc load to pull the j1850 bus down. if ground is lost, the transceiver releases the j1850 bus. the transceiver also protects the mcu interface by not passing on any disruptive signals that may be on the j1850 bus.
MC68HC58 introduction motorola technical data 1-3 figure 1-1 MC68HC58 dlc parallel mode block diagram b u s t r a n s c e i v e r oscillator mcu m c u i n t e r f a c e cs addr0 r/w int rst eclk parallel data data[7:0] osc1 osc2 power v dd v cc v batt v ssa v ssd p sen digital supply internal clock rx data tx data command & status control rx fifo tx fifo rx bit timing control & timing tx bit timing analog supply loti lito prlmd rext bus load dlc parallel mode block
motorola introduction MC68HC58 1-4 technical data figure 1-2 MC68HC58 dlc serial mode block diagram b u s t r a n s c e i v e r oscillator mcu m c u i n t e r f a c e cs simo int rst sclk osc1 osc2 power v dd v cc v batt v ssa v ssd p sen digital supply internal clock rx data tx data command & status control rx fifo tx fifo rx bit timing control & timing tx bit timing analog supply loti lito prlmd rext bus load dlc serial mode block somi
MC68HC58 signal and pin descriptions motorola technical data 2-1 section 2signal and pin descriptions the MC68HC58 dlc is available in a 28-pin plastic leaded chip carrier (plcc) pack- age and a 28-pin small outline integrated circuit (soic) package. the MC68HC58 is pin configurable to communicate with a host mcu via a serial or parallel interface. se- rial or parallel mode is selected by connecting the prlmd pin to ground or v dd re- spectively. pin function and recommended interconnections are discussed in the following paragraphs. refer to appendix b mechanical data and ordering information for information on package dimensions and ordering information. 2.1 MC68HC58 dlc parallel mode when the prlmd pin is tied to v dd , the MC68HC58 dlc communicates with the host mcu via a parallel interface. interface timing is based on the m6800 external bus clock signal (eclk). motorola m68hc11, m68hc16, and m68300 series mcus have eclk outputs, but any host mcu that meets the timing specification can be used. figure 2-1 is a pinout of the MC68HC58 (plcc). figure 2-1 MC68HC58 dlc pin assignments dlc (top view) v cc psen v batt bus load v ssd data0 rst cs *(sclk)/eclk *(simo)/addr0 *(somi)/r/w int v dd * () indicates pin assignments for serial mode operation data7 data6 data5 data4 data3 data2 data1 osc1 osc2 loti v ssa lito prlmd rext dlc pin assignment
motorola signal and pin descriptions MC68HC58 2-2 technical data 2.1.1 dlc parallel mode pin function table 2-1 summarizes dlc pin functions when operating in parallel mode. detailed discussion of each function follows. refer to appendix a electrical charac- teristics for more information on electrical specifications. 2.1.1.1 addr0 ?address bit this pin is used in conjunction with the r/w signal to address the dlc in the mcu memory map. although the name addr0 implies that the pin should be connected to address line 0, it can in fact be connected to any address line to place it at a desired location in memory. 2.1.1.2 bus ?sae j1850 multiplex bus this pin connects the dlc to the sae j1850 multiplex bus. the bus signal is driven to a nominal 7 vdc with respect to the bus load when in an active level; it is grounded through the bus load when in a passive level. 2.1.1.3 cs ?dlc chip-select this pin is used to input the dlc parallel data exchange enable signal. it has a nominal 15 k w internal pull-up resistor. table 2-1 MC68HC58 dlc parallel mode pin function name type function addr0 input address select signal bus input/output serial data signal cs input dlc chip-select signal data[7:0] input/output bidirectional three-state data bus eclk input 6800 bus clock int output dlc interrupt request lito input/output logic in transceiver out load input external bus load connection loti input/output logic out transceiver in osc1 input external clock connection osc2 output external reference connection psen output power supply status signal prlmd input parallel/serial mode select signal rext input transceiver biasing resistor rst input dlc reset signal r/w input dlc data transfer control v batt power supply transceiver power connection v cc power supply analog power connection v dd power supply digital power connection v ssa power supply analog ground v ssd power supply digital ground
MC68HC58 signal and pin descriptions motorola technical data 2-3 2.1.1.4 data[7:0] ?dlc data bus these pins are the bidirectional data lines used to transfer parallel bytes to and from the dlc. the data lines are in high-impedance state unless cs is asserted. 2.1.1.5 eclk ?6800 bus clock this pin is used to input a 6800 peripheral bus clock. clock timing controls parallel data exchange with the mcu. m68hc11, m68hc16, and m68300 mcus all provide clock outputs to facilitate connection of 6800-timed peripherals. 2.1.1.6 int ?dlc interrupt request this pin is used to output an open drain active-low interrupt request signal to the mcu. the signal is fully compatible with m68hc11, m68hc16, and m68300 interrupt re- quest inputs. int must have an external pull-up resistor. 2.1.1.7 lito ?logic in transceiver out this pin is an external tap on the internal receive signal sent from the transceiver to the control logic. it is used for testing only, and must be left unconnected for normal operation. 2.1.1.8 load ?external bus load this pin provides an internal ground connection for the sae j1850 multiplex bus load resistor. if dlc analog ground is lost, load goes to a high-impedance state. 2.1.1.9 loti ?logic out transceiver in this pin is an external tap on the internal transmit signal sent from the control logic to the transceiver. it is used for testing only, and must be left unconnected for normal op- eration. 2.1.1.10 osc1, osc2 ?external oscillator the dlc can operate with either an external clock signal or an external ceramic res- onator. these pins support connection of both types of clock. if an external clock source is used, the signal is input via osc1, and osc2 is left floating. if a resonator is used, it is connected between osc1 and osc2. 2.1.1.11 prlmd ?parallel mode this pin is used to select the desired mcu interface mode. when this pin is pulled up to v dd , the parallel mode is selected. 2.1.1.12 psen ?power supply enable this pin provides an external v batt source when the dlc is active. it assumes high- impedance state when the dlc is in standby mode.
motorola signal and pin descriptions MC68HC58 2-4 technical data 2.1.1.13 rst ?dlc reset this pin is used to input an active-low system reset signal. rst must have an external pull-up resistor. 2.1.1.14 rext ?external bias resistor this pin connects an external bias resistor to the transceiver. the resistor value deter- mines the waveform of the transmitted bus signal. 2.1.1.15 r/w ?read/write strobe this pin is used to input a data direction control signal to the dlc. this signal is used in conjunction with the addr0 signal to select the dlc at a specific address in the mcu memory map. 2.1.1.16 v batt ?battery voltage this pin connects a separate switched or unswitched 12 vdc power supply to the dlc bus transceiver. this supply should be well regulated and protected against switching transients. 2.1.1.17 v cc ?analog power supply voltage this pin connects a nominal 5 vdc power supply to the analog transceiver circuitry in the dlc. for maximum noise immunity, v cc supply path should be separate from v dd supply path . 2.1.1.18 v dd ?digital power supply voltage this pin connects a nominal 5 vdc power supply to the digital control circuitry in the dlc. for maximum noise immunity, the v dd supply path should be separate from v cc supply path . 2.1.1.19 v ssa ?analog power ground this pin provides the analog power ground connection to the dlc. loss of analog ground directly affects operation of the load pin. for best noise immunity in opera- tion, the v ssa ground path should be separate from the v ssd ground path . 2.1.1.20 v ssd ?digital power ground this pin provides the digital power ground connection to the dlc. for best noise im- munity in operation, the v ssd ground path should be separate from the v ssa ground path .
MC68HC58 signal and pin descriptions motorola technical data 2-5 2.1.2 example dlc parallel mode system figure 2-2 shows a typical dlc circuit (plcc). the component values displayed are recommended, although adjustment may be required in actual operation. the exam- ple is shown wired for low-power standby mode. typical m68hc11 mcu connections are shown, but any host mcu that has appropriate inputs and outputs compatible with dlc signals can be used. figure 2-2 dlc parallel mode circuit dlc (top view) 28-pin plcc data7 data6 data5 data4 data3 data2 data1 v cc psen v batt bus load v ssd data0 osc1 osc2 loti v ssa lito prlmd rext rst cs eclk addr0 r/w int v dd d7 d6 d5 d4 d3 d2 d1 d0 hc11 address address line(s) e a0 r/w irq v cc reset csio 0.1 m f 10 k w 10 k w +5v power supply vigin gnd connector ignition dlc parallel mode circuit dlc application first node all others r1 1.5 k w 10.6 k w c1 3300 pf 470 pf gnd battery transient protection decoupling 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0.1 m f v cc 0.1 m f 19 20 21 22 23 24 25 24.9 k w , 1% nc nc 4.00 mhz ceramic resonator 30 pf 30 pf 4 3 2 1 28 27 26 class 2 bus (j1850) r1 c1 l1 decoder 47 m h
motorola signal and pin descriptions MC68HC58 2-6 technical data the following additional guidelines apply to figure 2-2 : 1. pull-up resistor values depend on electrical characteristics of the host mcu. 2. exact values for the external components are a function of printed circuit board (pcb) capacitance and inductance, socket capacitance, operating voltage and crystal technology. 3. the example ceramic resonator is a murata csa4.00mga with typical load ca- pacitance. the dlc contains an internal 1 m w resistor across osc1 and osc2. no external resistor is required. 4. l1 is a surface mount inductor which should have characteristics similar to tdk nl322522t-470j-3. 5. the external bias resistor (rext) determines the waveshape of j1850 bus sig- nals transmitted by the dlc. 6. for maximum noise immunity, v cc and v dd should be supplied by separate lines; v ssa and v ssd should also be separate. the v batt pin is shown at- tached to the permanent ?nswitched?battery supply to take advantage of the better transient protection found on this circuit rather than the ?witched?bat- tery, or ignition. 7. applications whose requirements for electro-static discharge (esd) protection exceed the level provided by the bus pin internal circuitry and the bus loading components may require additional transient protection. the example in figure 2-2 illustrates this by including two 16 volt zener diodes placed between the bus and ground. these diodes (part # p4sma16at3) should be located as close to the module connector as possible. refer to appendix a electrical characteristics for information on maximum voltage ratings. 8. one j1850 node in the vehicle typically has a heavier bus to load pin loading. this allows a smaller differential between the total network load of two nodes versus 32 nodes. if 26 nodes or more are used, the heavier loading should not be present as this may violate the maximum capacitance and minimum resis- tance allowed by the j1850. a network of 26 or more nodes should all have the lower load values. 9. figure 2-2 reflects a configuration for no wake-up upon the detection of j1850 bus activity. if system wake-up upon the detection of j1850 bus activity is de- sired, perform the following: ?tie the v dd pin to a 5 vdc power supply. this 5 vdc power supply is powered down when the dlc is placed in the standby mode. ?tie the psen pin on the dlc through a 33 k w resistor to the ignition input of the power supply/regulator. this limits the current sourced by the dlc. this resistor value should be determined by the individual application. a 10 k w pull-down resistor should be included from the psen line to ground. a 100 k w resistor from the rst pin to ground should also be added. ?tie the v cc pin and the pull-up points for the external bias resistor (rext) on the dlc to a separate 5 vdc power supply. this 5 vdc power supply remains powered up when the rest of the node is powered down.
MC68HC58 signal and pin descriptions motorola technical data 2-7 2.2 MC68HC58 dlc serial mode the MC68HC58 dlc communicates with the host mcu via a standard serial periph- eral interface (spi) when in serial mode. interface timing is based on a serial clock sig- nal (sclk) provided by the host mcu. motorola m68hc05, m68hc11, m68hc16, and m68300 series mcus have spi capabilities, but any host mcu that meets the clock specification can be used. refer to figure 2-1 for serial mode pinout information. 2.2.1 dlc serial mode pin function table 2-2 summarizes dlc serial mode pin function. detailed discussion of each function follows. refer to appendix a electrical characteristics for more information on electrical specifications. 2.2.1.1 bus ?sae j1850 multiplex bus this pin connects the dlc to the sae j1850 multiplex bus. the bus signal is driven to a nominal 7 vdc with respect to the bus load in an active level; it is grounded through the bus load in a passive level. 2.2.1.2 cs ?dlc chip-select this pin is used to input the dlc serial data exchange enable signal. it has a nominal 15 k w internal pull-up resistor. table 2-2 MC68HC58 dlc serial mode pin functions name type function bus input/output serial bus connection cs input dlc chip-select signal int output dlc interrupt request lito input/output logic in transceiver out signal load input external bus load connection loti input/output logic out transceiver in signal osc1 input external clock connection osc2 output external reference connection psen output power supply status signal prlmd input parallel/serial mode select signal rext input transceiver biasing resistor rst input dlc reset signal sclk input spi serial clock simo input slave in master out signal somi output slave out master in signal v batt power supply transceiver power connection v cc power supply analog power connection v dd power supply digital power connection v ssa power supply analog ground v ssd power supply digital ground
motorola signal and pin descriptions MC68HC58 2-8 technical data 2.2.1.3 int ?dlc interrupt request this pin is used to output an open drain active-low interrupt request signal to the mcu. the signal is fully compatible with m68hc05, m68hc11, m68hc16, and m68300 in- terrupt request inputs. int must have an external pull-up resistor. 2.2.1.4 lito ?logic in transceiver out this pin is an external tap on the internal receive signal sent from the transceiver to the control logic. it is used for testing only, and must be left unconnected for normal operation. 2.2.1.5 load ?external bus load this pin provides an internal ground connection for the sae j1850 multiplex bus load resistor. if dlc analog ground is lost, load goes to a high-impedance state. 2.2.1.6 loti ?logic out transceiver in this pin is an external tap on the internal transmit signal sent from the control logic to the transceiver. it is used for testing only, and must be left unconnected for normal op- eration. 2.2.1.7 osc1, osc2 ?external oscillator the dlc can operate with either an external clock signal or an external ceramic res- onator. these pins support connection of both types of clock. if an external clock source is used, the signal is input via osc1, and osc2 is left floating. if a resonator is used, it is connected between osc1 and osc2. 2.2.1.8 prlmd ?arallel mode this pin is used to select the desired mcu interface mode. when this pin is pulled down from v dd , the serial mode is selected. 2.2.1.9 psen ?power supply enable this pin provides an external v batt source when the dlc is active. it assumes high- impedance state when the dlc is in standby mode. 2.2.1.10 rst ?dlc reset this pin is used to input an active-low system reset signal. rst must have an external pull-up resistor. 2.2.1.11 rext ?external bias resistor this pin connects an external bias resistor to the transceiver. the resistor value deter- mines the waveform of the transmitted bus signal.
MC68HC58 signal and pin descriptions motorola technical data 2-9 2.2.1.12 sclk ?serial clock this pin is used to input a serial clock signal to the dlc spi. this signal is generated by the spi bus master device (typically the mcu). 2.2.1.13 simo ?slave in master out the spi interface performs simultaneous bidirectional transfers initiated by a bus mas- ter. this pin connects the serial data input from the spi bus to the dlc (the dlc is an spi slave device). 2.2.1.14 somi ?slave out master in the spi performs simultaneous bidirectional transfers initiated by a bus master. this pin connects the serial data output from the dlc to the spi bus (the dlc is an spi slave device). 2.2.1.15 v batt ?battery voltage this pin connects a separate switched or unswitched 12 vdc power supply to the dlc bus transceiver. this supply should be well regulated and protected against switching transients. 2.2.1.16 v cc ?analog power supply voltage this pin connects a nominal 5 vdc power supply to the analog transceiver circuitry in the dlc. for maximum noise immunity, v cc supply path should be separate from v dd supply path . 2.2.1.17 v dd ?digital power supply voltage this pin connects a nominal 5 vdc power supply to the digital control circuitry in the dlc. for maximum noise immunity, the v dd supply path should be separate from v cc supply path . 2.2.1.18 v ssa ?analog power ground this pin provides the analog power ground connection to the dlc. loss of analog ground directly affects operation of the load pin. for best noise immunity in opera- tion, the v ssa ground path should be separate from the v ssd ground path . 2.2.1.19 v ssd ?digital power ground this pin provides the digital power ground connection to the dlc. for best noise im- munity in operation, the v ssd ground path should be separate from the v ssa ground path .
motorola signal and pin descriptions MC68HC58 2-10 technical data 2.2.2 example dlc serial mode system figure 2-3 displays a typical dlc serial mode circuit (plcc). the component values displayed are recommended, although adjustment may be required in actual opera- tion. the example is shown wired for low-power standby mode. typical m68hc11 mcu connections are shown, but any host mcu that has appropriate inputs and out- puts compatible with dlc signals can be used. figure 2-3 dlc serial mode circuit dlc (top view) 28-pin plcc v cc psen v batt bus load v ssd osc1 osc2 loti v ssa lito prlmd rext rst cs sclk simo somi int v dd hc11 sclk mosi miso irq v cc reset i/o pin 0.1 m f 10 k w 10 k w +5v power supply vigin gnd connector ignition dlc serial mode circuit dlc application first node all others r1 1.5 k w 10.6 k w c1 3300 pf 470 pf gnd battery transient protection decoupling 5 6 7 8 9 10 11 12 13 14 15 16 17 18 0.1 m f v cc 0.1 m f 19 20 21 22 23 24 25 24.9 k w , 1% nc nc 4.00 mhz ceramic resonator 30 pf 30 pf 4 3 2 1 28 27 26 class 2 bus (j1850) r1 c1 l1 47 m h
MC68HC58 signal and pin descriptions motorola technical data 2-11 the following additional guidelines apply to figure 2-3 : 1. pull-up resistor values depend on electrical characteristics of the host mcu. 2. exact values for the external components are a function of printed circuit board (pcb) capacitance and inductance, socket capacitance, operating voltage and crystal technology. 3. the example ceramic resonator is a murata csa4.00mga with typical load ca- pacitance. the dlc contains an internal 1 m w resistor across osc1 and osc2. no external resistor is required. 4. l1 is a surface mount inductor which should have characteristics similar to tdk nl322522t-470j-3. 5. an external bias resistor (rext) determines the waveshape of j1850 bus signals transmitted by the dlc. 6. for maximum noise immunity, v cc and v dd should be supplied by separate lines; v ssa and v ssd should also be separate. the v batt pin is shown at- tached to the permanent ?nswitched?battery supply to take advantage of the better transient protection found on this circuit rather than the ?witched?bat- tery, or ignition. 7. applications whose requirements for electro-static discharge (esd) protection exceed the level provided by the bus pin internal circuitry and the bus loading components may require additional transient protection. the example in figure 2-3 illustrates this by including two 16-volt zener diodes placed between the bus and ground. these diodes (part # p4sma16at3) should be located as close to the module connector as possible. refer to appendix a electrical characteristics for information on maximum voltage ratings. 8. one j1850 node in the vehicle typically has a heavier bus to load pin loading. this allows a smaller differential between the total network load of two nodes versus 32 nodes. if 26 nodes or more are used, the heavier loading should not be present as this may violate the maximum capacitance and minimum resis- tance allowed by the j1850. a network of 26 or more nodes should all have the lower load values. 9. although pins 12-19 of the dlc are used only for factory testing, it is recom- mended that these pins be tied to ground in the application. this prevents ad- ditional current from being consumed by the dlc, particularly when the low- power standby mode is utilized. 10. figure 2-3 reflects a configuration for no wake-up upon the detection of j1850 bus activity. if system wake-up upon the detection of j1850 bus activity is de- sired, perform the following: ?tie the v dd pin to a 5 vdc power supply. this 5 vdc power supply is powered down when the dlc is placed in the standby mode. ?tie the psen pin on the dlc through a 33 k w resistor to the ignition input of the power supply/regulator. this limits the current sourced by the dlc. this resistor value should be determined by the individual application. a 10 k w pull-down resistor should be included from the psen line to ground. a 100 k w resistor from the rst pin to ground should also be added. ?tie the v cc pin and the pull-up points for the external bias resistor (rext) on the dlc to a separate 5 vdc power supply. this 5 vdc power supply remains powered up when the rest of the node is powered down.
motorola signal and pin descriptions MC68HC58 2-12 technical data 2.3 bus loading the total load capacitance (c load ) on the j1850 vpw network, as specified in sae j1850, must be between 2470 pf and 16544 pf. likewise, the load resistance (r load ) on the network must be between 315 w and 1575 w . in addition, the network time constant (the product of r load and c load ) must not exceed 5.2 m s. it is recommended that in j1850 vpw systems with less than 26 nodes, one node should have a load capacitance of 3200 to 3300 pf and a load resistance of 1.5 k w , with all other nodes having the nominal load of 470 pf and 10.6 k w , as outlined in sae standard j1850 ?class b data communications network inter- face . this helps to minimize the differences in loading between small and large sys- tems. when there are more than 26 nodes in a system, the large single load should be replaced with a nominal load to avoid exceeding maximum capacitance and mini- mum resistance specifications. 2.4 dlc clock sources there are two types of clock signals associated with each dlc. the logic, or system clock, provides a reference frequency for internal operations and sae j1850 bus op- eration. host interface clocks provide timing for transfers between the dlc and the host mcu. 2.4.1 logic clock the dlc can operate with an external oscillator reference connected between osc1 and osc2, or with an external clock source applied to osc1 (osc2 left floating). in- ternal clock frequency is determined by the value of the configuration byte oscillator divisor (oscd) field. the dlc can be configured for divisor values of 1, 2, 3, or 4. re- gardless of external clock frequency, in order to operate properly, a dlc must be con- figured so that its internal clock frequency is 2 mhz. it is recommended that the dlc be clocked by a ceramic resonator. ceramic resona- tors stabilize much more rapidly than crystal references (typically, 100 times faster), and are less expensive, although they may have looser frequency tolerance. the dlc can be configured to operate with 2, 4, 6, or 8 mhz resonators. the dlc can operate with external clock input frequencies of 2, 4, 6, or 8 mhz. refer to appendix a electrical characteristics for more information. 2.4.2 host interface clock host interface circuitry within each type of dlc is clocked by a source in the host mcu. when operating in parallel mode, the dlc is clocked by an m6800 bus clock signal (clk). in serial mode, the dlc is clocked by an spi serial clock signal. either of the interface clocks can have any frequency from dc to 4.2 mhz. duty cycle must be 50% 5%. the clocks need only be active during the time that the dlc cs signal is asserted. refer to section 4 data link controller operation for more information on host mcu clocking.
MC68HC58 signal and pin descriptions motorola technical data 2-13 2.5 power supply connections during standby mode, the dlc oscillator and most internal circuitry are inactive. pow- er consumption is reduced significantly. the host mcu must send the dlc a command byte to initiate low power operation, but the dlc can be reactivated in a number of ways. a dlc can come out of standby when it detects j1850 bus activity, when its status register is read by the host mcu, or when power is applied. if interrupts are enabled, the dlc can issue an interrupt re- quest to the host mcu when it is activated. the way in which power is applied to the dlc affects activation out of standby mode. ignition switch position, battery drain during engine cranking, and alternator power sta- bility can affect the supplies available at the time j1850 bus activity brings the dlc out of standby mode. there are three recommended methods of implementing operation. methods 1 and 2 permit the receiver to be activated by a frame on the j1850 bus. with a 4 or 8 mhz resonator, a properly configured dlc can accurately receive the frame that activates it. if interrupts are enabled, methods 1 and 3 permit the dlc to generate an interrupt request upon activation. method 2 does not permit the dlc to generate an interrupt request when it is activated, because the control logic is not powered when j1850 bus activity is detected. refer to section 4 data link controller operation for more information on dlc interrupt service requests.
motorola signal and pin descriptions MC68HC58 2-14 technical data 2.5.1 method 1 ?all supplies applied when v batt , v cc , and v dd are applied, the psen pin goes to a high-impedance state when the dlc is in standby mode, and sources 12 vdc when the dlc is activated. figure 2-4 shows j1850 bus, int , rst , and psen timing relationships. if the host does not service the interrupt due to bus activity, the dlc automatically re-enters standby mode. refer to appendix a electrical characteristics for more information on parameter specifications. figure 2-4 method 1 ?standby mode supplies applied 12v 0v 5v 5v 0v 0v active passive t acint 5v 0v 12v 0v high impedance high impedance standby normal standby v batt v cc /v dd rst bus int psen dlc mode dlc pmc1
MC68HC58 signal and pin descriptions motorola technical data 2-15 2.5.2 method 2 ?switching v dd with psen with v batt and v cc applied, the psen pin goes to a high-impedance state when the dlc is in standby mode and sources 12 vdc when the dlc detects j1850 bus activity. refer to 2.6 reset for more information on supply stabilization. figure 2-5 shows bus, int , rst , and psen timing relationships. refer to appendix a electrical characteristics for more information on parameter specifications. figure 2-5 method 2 ?switching v dd with psen 12v 0v 5v 5v 0v 0v active passive t acdly 5v 0v 12v 0v standby normal standby v batt v cc rst bus int psen dlc mode dlc pmc2 v dd 5v 0v standby high impedance high impedance reset standby reset
motorola signal and pin descriptions MC68HC58 2-16 technical data 2.5.3 method 3 ?switching v dd and v cc simultaneously when v batt alone is applied, the psen pin stays in a high-impedance state until v dd and v cc are applied. applying v dd and v cc simultaneously (using a common 5 vdc supply) activates the dlc and causes the psen pin to source 12 vdc. if this method is chosen, the dlc is not affected by bus activity. figure 2-6 shows bus, int , rst , and psen timing relationships. refer to appendix a electrical character- istics for more information on parameter specifications. figure 2-6 method 3 ?switching v dd and v cc in standby mode 12v 0v 5v 5v 0v 0v 5v 0v 12v 0v power off normal power off v batt v cc /v dd rst int psen dlc mode dlc pmc3 reset reset high impedance high impedance
MC68HC58 signal and pin descriptions motorola technical data 2-17 2.6 reset while the rst signal is asserted, the dlc is held in an inactive state. the dlc is ac- tivated when the rst line goes high. when exiting the low-power standby mode, all system power must be applied and stable at the time rst goes high in order for the dlc to be properly activated. during reset, all data in the dlc fifo buffers is lost. many mcus have low-power standby modes that permit them to remain inactive until needed. these devices typically exit low-power stop when reset, or when an interrupt request is received. if the host mcu, as well as the dlc, are to be activated when the dlc detects j1850 bus activity, use of a common reset line may cause the frame that activates the system to be lost. after the reset line goes high, the host mcu writes command and configuration bytes to the dlc to initialize it. the ?oad as configuration byte ?immediate?command should be issued to initialize the dlc. the host may commence further operations with the dlc (t con ) afterwards. refer to appendix a electrical characteristics for more information on parameter specifics. refer to section 4 data link con- troller operation for more information on system initialization and configura- tion.
motorola signal and pin descriptions MC68HC58 2-18 technical data
MC68HC58 j1850 frame format motorola technical data 3-1 section 3 j1850 frame format this section explains the frame format used to transmit and receive information on the j1850 bus. variable pulse width modulation (vpw) valid/invalid bits and symbols are also discussed. 3.1 j1850 frame format a j1850 bus message consists of one or more frames. each frame is composed of multiple symbols. refer to figure 3-1 . figure 3-1 j1850 bus message components a symbol starts with a transition from either an active to a passive level, or a passive to an active level. symbols end with another transition, or the absence of a transition after a specified time period. figure 3-2 illustrates the representative symbols for a j1850 message frame. figure 3-2 j1850 bus frame format (vpw) message frame frame frame symbols symbols symbols j1850 bus mess comp sof eof data n crc ifr idle idle optional data 1 data 0 nb j1850 bus frame format e o d i f s
motorola j1850 frame format MC68HC58 3-2 technical data variable pulse width (vpw) modulation is an encoding technique in which each bit is defined by the time between successive transitions, and by the level of the j1850 bus between transitions. the non-destructive contention protocol on the j1850 bus defines both active and pas- sive symbols. active and passive bits are used alternately. a symbol is active when one or more transmitters drive the j1850 bus. a symbol is passive when no transmit- ters are driving the j1850 bus (a logical wired-or arrangement). each logic one or logic zero contains a single transition, and can be at either the active or passive level and one of two lengths, either 64 m s or 128 m s (t nom at 10.4 kbps baud rate), depending upon the encoding of the previous bit. the sof, eod, eof and ifs symbols are always encoded at an assigned level and length. for an illustration of vpw symbol timing, refer to figure 3-3 . each frame has a maximum length of 12 bytes, excluding the start of frame (sof), end of data (eod), normalization bit (nb), and end of frame (eof) symbols. each frame begins with an sof symbol, an active symbol, and therefore each data byte (including the crc byte) begins with a passive bit, regardless of whether it is a logic one or a logic zero. all vpw bit lengths stated in the following descriptions are typical values at a 10.4 kbps bit rate. 3.1.1 sof ?start of frame symbol all frames transmitted onto the j1850 bus must begin with an sof symbol. this indi- cates to any listeners on the j1850 bus the start of a new frame transmission. the sof symbol is not used in the cyclical redundancy check (crc) calculation. the sof symbol is defined as a passive to active transition followed by an active pe- riod 200 m s in length. refer to figure 3-3 (c). this allows the data bytes which follow the sof symbol to begin with a passive bit, regardless of whether it is a logic one or a logic zero. 3.1.2 data ?in frame data bytes the data bytes contained in the frame include the frame header bytes and any actual data being transmitted to the receiving node. the dlc can be used to transmit frames using any of the header formats outlined in the sae j1850 document. refer to the sae j1850 ?class b data communications network interface for more information about j1850 header formats. each data byte is made up of a series of logic one and logic zero symbols. frames transmitted by the dlc onto the j1850 bus must contain at least one data byte, and therefore can be as short as one data byte and one crc byte. each data byte in the frame is eight bits in length, transmitted most significant bit (msb) to least significant bit (lsb).
MC68HC58 j1850 frame format motorola technical data 3-3 3.1.2.1 logic zero a logic zero is defined as either an active to passive transition followed by a passive period 64 m s in length, or a passive to active transition followed by an active period 128 m s in length. refer to figure 3-3 (a). 3.1.2.2 logic one a logic one is defined as either an active to passive transition followed by a passive period 128 m s in length, or a passive to active transition followed by an active period 64 m s in length. refer to figure 3-3 (b). 3.1.3 crc ?cyclical redundancy check byte the crc byte is used by the receiver(s) of each frame to determine if any errors have occurred during the transmission of the frame. the dlc calculates the crc byte and appends it onto any frames transmitted onto the j1850 bus, and also performs crc detection on any frames it receives from the j1850 bus. crc generation uses the divisor polynomial x 8 +x 4 +x 3 +x 2 +1. the remainder polyno- mial is initially set to all ones, and then each byte in the frame after the sof symbol is serially processed through the crc generation circuitry. the one? complement of the remainder then becomes the 8-bit crc byte, which is appended to the frame after the data bytes, in msb to lsb order. when receiving a frame, the dlc uses the same divisor polynomial. all data bytes, excluding the sof and eod symbols, but including the crc byte, are used to check the crc. if the frame is error free, the remainder polynomial equals x 7 +x 6 +x 2 ($c4), regardless of the data contained in the frame. if the calculated crc does not equal $c4, the dlc informs the cpu of the failure. 3.1.4 eod ?end of data symbol the eod symbol is a passive period on the j1850 bus used to signify to any recipients of a frame that the transmission by the originator has been completed. the eod symbol is defined as an active to passive transition followed by a passive period 200 m s in length. refer to figure 3-3 (d and e). 3.1.5 nb ?normalization bit the nb is used to preface the in-frame response (ifr). the nb ensures that the end of the eighth bit of the ifr always returns the bus to the passive level. the length of the nb may be used to signify the type of ifr being used. the nb is transmitted by the node responding to the frame, and it defines the start of the optional response seg- ment, if utilized, of any vpw format frame. the dlc indicates that the ifr being trans- mitted has a crc appended by using a logic one (active short) bit. the dlc indicates that it does not contain a crc by using a logic zero (active long) bit.
motorola j1850 frame format MC68HC58 3-4 technical data note this method of crc recognition is the reverse of the method pre- ferred by the sae j1850. 3.1.6 ifr ?in-frame response bytes a number of options are available in the ifr section of the j1850 frame format. the dlc can send an ifr consisting of one or more bytes, which may be followed by a crc byte. 3.1.7 eof ?end of frame symbol the eof symbol is a passive period on the j1850 bus, longer than an eod symbol, which signifies the end of a frame. since an eof symbol is longer than an eod sym- bol, if no response is transmitted after an eod symbol, it becomes an eof, and the frame is assumed to be completed. the eof symbol is defined as an active to passive transition followed by a passive period of at least 280 m s in length. refer to figure 3-3 (e). if there is no ifr byte trans- mitted after an eod symbol is transmitted, after another 80 m s the eod becomes an eof, indicating the completion of the frame. 3.1.8 ifs ?inter-frame separation symbol the ifs symbol is a passive period on the j1850 bus which allows proper synchroni- zation between nodes during continuous frame transmission. the ifs symbol is trans- mitted by a node following the completion of the eof period. when the last byte of a frame has been transmitted onto the j1850 bus, and the eof symbol time has expired, all nodes must then wait for the ifs symbol time to expire before transmitting an sof, marking the beginning of another frame. however, if the dlc is waiting for the ifs period to expire before beginning a trans- mission and a passive to active level is detected before the ifs time has expired, it must internally synchronize to that edge. a passive to active level may occur during the ifs period because of varying clock tolerances and loading of the j1850 bus, causing different nodes to observe the completion of the ifs period at different times. receivers must synchronize to any sof occurring during an ifs period to allow for individual clock tolerances. the ifs symbol is defined as an active to passive transition followed by a passive period 300 m s in length. refer to figure 3-3 (e). 3.1.9 break ?break any dlc transmitting at the time a break symbol is detected halts transmission im- mediately, and indicates to the host mcu that a break was detected. the dlc can also transmit a break symbol if necessary. the break signal is defined as a passive to active transition followed by an active period of at least 239 m s. refer to figure 3-3 (f).
MC68HC58 j1850 frame format motorola technical data 3-5 3.1.10 idle bus an idle condition exists on the j1850 bus after expiration of the ifs period. any node sensing an idle bus condition can begin transmission immediately. figure 3-3 j1850 vpw symbols 3.2 j1850 vpw valid/invalid bits and symbols the timing tolerances for receiving data bits and symbols from the j1850 bus allow for variations in the system. the tolerances are balanced by making the maximum of one symbol length approximately equal to the minimum length of the next longest symbol. the difference between the symbol boundaries is equal to one clock period of the dlc internal clock. 128 m s active passive 64 m s or logic ? 128 m s active passive 64 m s or logic ? 200 m s active passive sof 200 m s eod active passive 3 239 m s break (a) (b) (c) (d) (e) (f) last transition of frame ifs eof eod 300 m s 280 m s 200 m s j1850 vpw symbols
motorola j1850 frame format MC68HC58 3-6 technical data figure 3-4 displays the j1850 passive to active transition symbols. figure 3-5 displays the j1850 active to passive transition symbols. figure 3-4 j1850 vpw passive symbols b cd c b de active passive active passive active passive active passive a 280 m s 200 m s 128 m s 64 m s 300 m s fg ef active passive active passive (1) invalid passive bit - a to b (2) valid passive logic zero - b to c (3) valid passive logic one - c to d (4) valid eod symbol - d to e (5) valid eof symbol - e to f (6) valid eof + ifs symbol - f to g j1850 passive symbols
MC68HC58 j1850 frame format motorola technical data 3-7 3.2.1 invalid passive bit if the passive to active transition beginning the next data bit or symbol occurs between a (the active to passive transition beginning the current data bit or symbol) and b, the current bit is invalid. refer to figure 3-4 (1). 3.2.2 valid passive logic zero if the passive to active transition beginning the next data bit or symbol occurs between b and c, the current bit is considered a logic zero. refer to figure 3-4 (2). 3.2.3 valid passive logic one if the passive to active transition beginning the next data bit or symbol occurs between c and d, the current bit is considered a logic one. refer to figure 3-4 (3). 3.2.4 valid eod symbol if the passive to active transition beginning the next data bit or symbol occurs between d and e, the current symbol is considered a valid eod symbol. refer to figure 3-4 (4). 3.2.5 valid eof and ifs symbol if the passive to active transition beginning the sof symbol of the next frame occurs between e and f, the current symbol is considered a valid eof symbol. if the passive to active transition beginning the sof symbol of the next frame occurs between f and g, the current symbol is considered a valid eof symbol, followed by a valid ifs sym- bol. all nodes must wait until a valid ifs symbol time has expired before beginning transmission. however, due to variations in clock frequencies and j1850 bus loading, some nodes may recognize a valid ifs symbol before others, and immediately begin transmitting. therefore, any time a node waiting to transmit detects a passive to active transition once a valid eof has been detected, it should immediately begin transmis- sion, initiating the arbitration process. refer to figure 3-4 (5 and 6). 3.2.6 idle bus if the passive to active transition beginning the sof symbol of the next frame does not occur before g, the j1850 bus is considered to be idle, and any node wishing to trans- mit a frame may do so immediately. refer to figure 3-4 (6). 3.2.7 invalid active bit if the active to passive transition beginning the next data bit or symbol occurs between a (the passive to active transition beginning the current data bit or symbol) and b, the current bit is invalid. refer to figure 3-5 (1).
motorola j1850 frame format MC68HC58 3-8 technical data figure 3-5 j1850 vpw active symbols 3.2.8 valid active logic one if the active to passive transition beginning the next data bit or symbol occurs between b and c, the current bit is considered a logic one. refer to figure 3-5 (2). 3.2.9 valid active logic zero if the active to passive transition beginning the next data bit or symbol occurs between c and d, the current bit is considered a logic zero. refer to figure 3-5 (3). b cd c b 64 m s 128 m s e 200 m s ef d 280 m s a (1) invalid active bit - a to b (2) valid active logic one - b to c (3) valid active logic zero - c to d (4) valid sof symbol - d to e (5) valid break symbol - e to f active passive active passive active passive active passive active passive j1850 active symbols
MC68HC58 j1850 frame format motorola technical data 3-9 3.2.10 valid sof symbol if the active to passive transition beginning the next data bit or symbol occurs between d and e, the current symbol is considered a valid sof symbol. refer to figure 3-5 (4). 3.2.11 valid break symbol if the next active to passive transition does not occur between e and f, the current symbol is considered a valid break symbol. following the break symbol, an ifs period must be observed, after which normal communication can resume on the j1850 bus. refer to figure 3-5 (5). 3.3 frame arbitration frame arbitration on the j1850 bus is accomplished in a non-destructive manner, al- lowing the frame with the highest priority to be transmitted. transmitters which lose ar- bitration simply stop transmitting and wait for an idle j1850 bus to begin transmitting again. if the dlc wishes to transmit onto the j1850 bus, but detects that another frame is in progress, it must wait until the j1850 bus is idle. however, if multiple nodes begin to transmit in the same synchronization window, frame arbitration occurs beginning with the first bit after the sof symbol, and continues with each bit thereafter. the vpw symbols and j1850 bus electrical characteristics are carefully chosen so that a logic zero (active or passive type) always dominates over a logic one (active or passive type) simultaneously transmitted. hence logic zeros are said to be ?ominant and logic ones are said to be ?ecessive? whenever a node detects a dominant bit when it transmitted a recessive bit, it loses arbitration, and immediately stops transmit- ting. this is known as ?itwise arbitration? refer to figure 3-6 . figure 3-6 j1850 vpw bitwise arbitration transmitter a transmitter b j1850 bus sof data bit 1 data bit 4 data bit 5 ? transmitter a detects an active state on the bus, and stops transmitting transmitter b wins passive active passive active passive active ? ? ? ? ? data bit 2 ? ? ? data bit 3 ? ? ? ? ? arbitration and continues transmitting j1850 bit arb
motorola j1850 frame format MC68HC58 3-10 technical data during arbitration, or even when the frame is being transmitted, if an opposite bit (a dominant bit when a recessive bit is transmitted, or a recessive bit when a dominant bit is transmitted) is detected, transmission is immediately stopped unless it occurs on the eighth bit of the fourth or later bytes. in this case, the dlc automatically appends up to two extra 1 bits, then stops transmitting. these two extra 1 bits are arbitrated nor- mally, and do not interfere with another frame. the second 1 bit is not sent if the first loses arbitration. if the dlc loses arbitration to another valid frame, the two extra 1 bits do not corrupt the current frame. however, if the dlc has lost arbitration due to noise on the j1850 bus, the two extra 1 bits ensure that the current frame is detected and ignored as a noise-corrupted frame. since a zero dominates a one, the frame with the lowest value has the highest priority, and always wins arbitration (a frame with priority 000 wins arbitration over a frame with priority 001). this method of arbitration works no matter how many bits of priority en- coding are contained in the frame. if the dlc loses arbitration during the transmission of a frame, it attempts to retransmit as soon as a valid ifs is detected on the j1850 bus. the dlc attempts to retransmit the frame indefinitely, as long as frames with higher priorities continue to win arbitra- tion. the host mcu can terminate the transmission by transmitting the ?erminate auto retry?command to the dlc.
MC68HC58 data link controller operation motorola technical data 4-1 section 4 data link controller operation this section explains the operation of the MC68HC58 dlc. sae j1850 bus interface and general operation is the same for both the parallel and serial modes, but the meth- od of transferring information between the host mcu and the dlc differs. separate discussions of serial and parallel host mcu interfaces follow the general topics. sec- tion 5 control and status codes examines the specific information ex- changed by the host mcu and the dlc. 4.1 operating modes the dlc has six main modes of operation which interact with the power supplies, the j1850 bus interface, and the host mcu interface. refer to figure 4-1 . figure 4-1 dlc operating modes v dd > v dlc (min.) power off reset 4x mode normal v dd v dlc (min.) (from any mode) standby rst asserted reset asserted block mode host sends ?nter standby mode?command host fills txfifo without indicating last byte host sends ?oad as last byte?command host loads normal mode bit combination/ host loads 4x mode bit combination network activity/host reads status byte reset negated/configuration byte loaded into device dlc op modes reception of break symbol on bus
motorola data link controller operation MC68HC58 4-2 technical data 4.1.1 power-off mode power-off mode is entered whenever the dlc digital supply voltage v dd drops below the minimum specified value to guarantee correct dlc operation. this includes any standby mode where the v dd supply is switched off. in this mode, the input and output specifications of the host interface signals are not guaranteed. 4.1.2 reset mode reset mode is entered from the power-off mode whenever the dlc supply voltage v dd rises above the minimum specified value and the dlc rst input is asserted. reset mode is also entered from any other mode as soon as the dlc rst is asserted. during reset mode, the internal dlc voltage references are operative. v dd is supplied to the internal circuits, which are held in their reset state. the internal dlc system clock continues to run. registers assume their reset condition. outputs are held in their programmed reset state, inputs and network activity are ignored. 4.1.3 normal mode normal mode is entered from the reset mode after the dlc rst is negated, and the host loads a configuration byte into the dlc. normal mode is entered from the standby mode whenever network activity is sensed, or the host reads the dlc status byte. normal mode is entered from the 4x mode when a break symbol is received from the j1850 bus, or the host mcu clears the 4x mode bit in the configuration register. normal mode is entered from block mode when the host sends the ?oad as last byte of transmit data?command. during normal mode, normal network operation takes place. the user should ensure that all dlc transmissions have ceased before exiting this mode. 4.1.4 standby mode standby mode is entered when the host sends an ?nter standby mode?command. during standby mode, the dlc internal clocks are halted and the physical interface circuitry is placed in a low power mode to await network or host activity. 4.1.5 4x mode 4x mode is entered when the host loads the 4x mode bit configuration into the config- uration byte. during 4x mode, transceiver waveshaping is disabled, thus allowing the dlc to oper- ate without any slew rate limitation. 4x mode affects only the transmitted and received symbol timing logic of the dlc (including the digital filter).
MC68HC58 data link controller operation motorola technical data 4-3 4x mode allows communication on the multiplex bus to be performed at four times the normal bit rate. this high speed transfer function does not work properly unless all transmitting nodes on the j1850 bus are in 4x mode. selected receivers may be configured to ignore high speed frames until a break symbol is received. detection of a break symbol on the j1850 bus returns the dlc to normal mode. refer to 4.6 break operation for more information. 4.1.6 block mode block mode is entered when the host fills the transmit first in/first out (txfifo) buffer without indicating the last byte of a message. during block mode, the terminate auto retry function is automatically enabled. the dlc continues to transmit message bytes as long as the host loads message bytes into the txfifo buffer without sending the dlc a ?oad as last byte of transmit data command. the receive first in/first out (rxfifo) buffer is designed to allow the reception of block mode messages automatically. refer to 4.5 block mode operation for information. 4.2 host interface figure 4-2 shows typical usage of a dlc with an mcu. figure 4-2 dlc usage dlc usage r l c l mcu spi or parallel dlc load bus sae j1850 bus
motorola data link controller operation MC68HC58 4-4 technical data the data link controller exchanges information in pairs of bytes in both the serial and parallel modes. a standard exchange consists of one status byte and one data byte sent from the dlc to the host, and one data byte and one command byte sent from the host to the dlc. in serial mode, the host and the dlc exchange pairs of bytes simultaneously, while exchanges in parallel mode are sequential. a host can write contiguous data bytes to the dlc in parallel mode without intervening command bytes, provided the first and last data bytes are accompanied by ?oad as first byte of transmit data? ?oad as last byte of transmit data? or ?oad as first and last byte of transmit data?command bytes. data that the dlc receives from the host can be data for transmission on the sae j1850 bus, a configuration byte, or a null byte. the destination of a byte written to a dlc is specified in the command byte that accompanies it. command bytes can also contain dlc receive, transmit, and mode control instructions. the status byte that the host receives from the dlc contains information about the ac- companying data byte, current status of the transmitter, and current status of the re- ceiver. the data byte can contain received frame data, a transmission completion code, or invalid information. the dlc must be configured after power-up or reset, and at appropriate intervals thereafter. to configure a dlc, the host mcu sends a configuration command byte followed by a configuration data byte. mode of operation, clock speed, and interrupt mode are determined by the content of the configuration byte. when the cs signal is asserted, interface lines (parallel or serial) are enabled, then status and data words are prepared for transfer to the host. parallel transfers are controlled by the addr0, clk, and r/w signals. serial transfers are clocked by the sclk signal. when cs is released, interface lines are disabled and go to a high-im- pedance state. when interrupts are enabled, the dlc generates an interrupt based on four, or option- ally five interrupt sources. when one of these interrupt conditions occurs, the dlc as- serts the int output to request service from the host. the int output is negated when cs is asserted by the host and the status byte is read. refer to 4.2.3 interrupt re- quests for more information. figure 4-3 shows typical dlc operation.
MC68HC58 data link controller operation motorola technical data 4-5 figure 4-3 dlc operation the host mcu can put a dlc in standby mode by sending it the ?nter standby mode command byte. the dlc completes all current frames, then goes inactive. psen sources v batt while the dlc is active and goes to a high-impedance state during standby mode. an incoming bus frame, or the host mcu asserting cs and reading the status byte, can reactivate a dlc. 4.2.1 MC68HC58 dlc parallel mode host mcu interface the dlc interface is designed to work with an m6800 bus clock signal (clk), but functions equally well with any host mcu that meets timing requirements. refer to ap- pendix a electrical characteristics for more parallel host interface timing information. 4.2.1.1 parallel mode data transfer parallel mode transfers are controlled by the r/w and addr0 signals from the host mcu. r/w and addr0 determine which of four possible bytes are being transferred. figure 4-4 shows the parallel mode byte format. host interface host interface activity to transfer message into dlc for transmission host interface activity to transfer received message out of dlc last byte of message and completion code placed in rxfifo interrupt asserted bus interrupt line int bytes transmitted, message on bus interrupt cleared by cs and status read cs host interface activity bus activity dlc operation received, and placed into rxfifo
motorola data link controller operation MC68HC58 4-6 technical data figure 4-4 parallel mode byte format dlc command bytes are transferred before the accompanying data byte. when using the parallel host interface, the dlc requires command bytes only for the first and last byte(s) in a frame. a dlc command byte must be accompanied by another byte (data, null, or configuration) in order for the command to be latched. a command byte is not required to load each data byte into the txfifo buffer, but a data byte is required for a command to execute. table 4-1 shows the types of parallel transfers. the status byte value is frozen while cs is asserted. any changes that occur while cs is asserted are reflected in the status byte when cs is next asserted. the dlc interrupt request line is cleared when cs is asserted and the status byte is read. when cs is negated, the dlc parallel lines are disabled, and go into a high im- pedance state. 4.2.1.2 servicing sequence the host mcu services the dlc in the following sequence: 1. read status byte. 2. read receive data (if required). 3. write command byte. 4. write transmit data, configuration, or null byte (if preceded by command byte). the four operations form a complete service sequence. however, all four operations are not required in every host/dlc transfer. table 4-1 parallel transfers addr0 r/w type of transfer 0 0 command byte 0 1 status byte 1 0 transmit byte or configuration byte 1 1 receive byte or completion code command byte[7:0] addr0 r/w =0 r/w =1 dlc parallel byte format status byte[7:0] transmit byte[7:0] receive byte[7:0]
MC68HC58 data link controller operation motorola technical data 4-7 the host mcu can read only the status byte, or can read the status byte followed by a read of a data byte (the data read automatically flushes the associated data byte from the rxfifo buffer). there is no specified maximum time between reading of a status byte and reading of a data byte, but correct status of the rxfifo is guaranteed only for 1 m s. the dlc allows a host to write contiguous frame bytes to the txfifo buffer without intervening command bytes, provided that the first and last data bytes are accompa- nied by ?oad as first byte of transmit data? ?oad as last byte of transmit data? or ?oad as first and last byte of transmit data?command bytes. a data, configuration, or null byte need not immediately follow the associated command, but must be the next byte transferred to the dlc. the command byte is acted upon when the subsequent byte is written into the dlc. 4.2.1.3 minimum time requirements minimum time constraints appear on certain sequences of operations. table 4-2 shows the minimum time required between these operations. the left column shows initial operations; the top row, subsequent operations. 4.2.1.4 motorola microcontroller data transfers many motorola microcontroller families, including the m68hc11, m68hc16, and m68300 series mcus, can generate synchronous addr0, data, clk and r/w sig- nals. for example, host mcus based on m68hc11 microcontrollers can use instructions that load 16-bit double accumulator d from two consecutive byte addresses (ldd), and store accumulator content into two consecutive byte addresses (std). host mcus based on m68hc16 and m68300 microcontrollers can use the dynamic bus sizing capability to automate the transfer of 16-bit data to and from an 8-bit port. notes: 1. during block transfers only. 2. status valid for 1 m s table 4-2 minimum time between operations write command write data/config read status read data write command not allowed 0 not allowed not allowed write data/config 3 m s 3 m s 1 3 m s not allowed read status 0 not allowed 0 2 0 read data 3 m s not allowed 0 not allowed
motorola data link controller operation MC68HC58 4-8 technical data 4.2.2 MC68HC58 dlc serial mode host mcu interface in serial mode, the MC68HC58 dlc communicates with the host mcu via the spi. the spi performs simultaneous bidirectional transfers initiated by an spi bus master, with the dlc functioning as an spi slave device. spi transfers are timed by the sclk signal from the host mcu. all motorola mcu families (m68hc05, m68hc08, m68hc11, m68hc12, m68hc16, m68300 and mpc500) have devices with spi ca- pabilities, but any host mcu that meets the clock specification can be used. refer to appendix a electrical characteristics for more information. 4.2.2.1 serial mode data transfer data is always transferred between the host mcu and the dlc in a two byte format, with an optional delay between bytes for data management. this delay can be omitted if the host is utilizing a 16-bit shift register. the cs signal must remain asserted throughout the duration of the 16-bit transfer. while the host mcu is transmitting a data byte to the dlc, the dlc is transmitting a status byte to the host mcu. this status byte updates the host mcu as to the status of the dlc and its fifo buffers. the host mcu then transmits a command byte to the dlc, which tells the dlc what to do with the preceding data byte, while the dlc trans- mits a data byte to the host mcu. in the dlc, when the rfs field indicates that a com- pletion code is at the head of the buffer, the accompanying data byte contains that same completion code. the command, status and data bytes are ordered msb-to-lsb, and are transmitted in the non-return to zero (nrz) bit format. figure 4-5 shows the dlc serial mode byte format. figure 4-5 dlc serial mode byte format t7 t6 t5 t4 t3 t2 t1 t0 c7 c6 c5 c4 c3 c2 c1 c0 transmit byte command byte sclk simo optional delay for data management s7 s6 s5 s4 s3 s2 s1 s0 r7 r6 r5 r4 r3 r2 r1 r0 status byte receive byte somi dlc serial mode byte format
MC68HC58 data link controller operation motorola technical data 4-9 table 4-3 shows the types of serial transfers. 4.2.2.2 servicing sequence for every byte transmitted from the host to the dlc, there is a byte transferred from the dlc to the host. each data byte sent to the dlc is accompanied by a status byte that is sent to the host. each command byte sent to the dlc is accompanied by a re- ceived data byte that is sent to the host. the host mcu services the dlc in the following sequence: 1. read status byte and data byte. 2. write data byte, configuration byte, or null byte and command byte. received data remains in the rxfifo buffer until a flush byte command is received. however, the flush command can accompany the read command. each transmit data byte must be accompanied by a command byte that designates it as a first, intermedi- ate, or last byte. 4.2.2.3 spi exchange the host mcu controls sclk polarity and phase. the dlc is compatible with two sclk configurations: ?sclk polarity normally high, read data on sclk passive to active level, change data on sclk active to passive level. ?sclk normally low, read data on sclk passive to active level, change data on sclk active to passive level. the general format of the data exchange from the dlc to the host mcu is a bit-for-bit exchange on each sclk clock pulse. data is read in on the passive to active level of the sclk, and is changed on the active to passive level of sclk. the most significant bit of a transfer is sent first. figure 4-6 shows a 16-bit data transfer with low clock po- larity. figure 4-7 shows a 16-bit data transfer with high clock polarity. note this 16-bit transfer can be performed using two 8-bit transfers as long as cs is asserted before the first 8-bit transfer begins, and re- mains asserted until the end of the second 8-bit transfer. table 4-3 serial transfers 1st byte 2nd byte type of transfer simo command byte somi status byte simo transmit byte, configuration byte, or null byte somi receive byte, completion code, or null byte
motorola data link controller operation MC68HC58 4-10 technical data figure 4-6 spi transfer ?clock polarity low figure 4-7 spi transfer ?clock polarity high 4.2.2.4 initialization before the dlc is used for transmission or reception, it must be initialized. initialization is performed by loading a configuration data byte into the configuration byte register with the ?oad as configuration byte?mmediate?command. once the configuration byte is loaded following a reset of the dlc, the host can load message bytes to be transmitted onto the j1850 bus into the dlc. transmission will not begin until the dlc determines that an idle bus condition exists on the j1850 bus. figure 4-8 illustrates a basic host/dlc initialization routine. note use the ?oad as configuration byte?mmediate?command byte bit combination only after a reset, for test purposes, or for changing the interrupt mode or mask during normal operation. in the absence of these conditions, use the ?oad as configuration byte?command. cs somi sclk simo s7 s6 s5 s4 s3 s2 s1 s0 r7 r6 r5 r4 r3 r2 r1 r0 x7 x6 x5 x4 x3 x2 x1 x0 c7 c6 c5 c4 c3 c2 c1 c0 command byte latched in at this point, and its contents will be acted on within 2 m s data valid in this time period note: sclk normally low (polarity = 0), phase = 0 dlc spi transfer 1 cs somi sclk simo s7 s6 s5 s4 s3 s2 s1 s0 r7 r6 r5 r4 r3 r2 r1 r0 x7 x6 x5 x4 x3 x2 x1 x0 c7 c6 c5 c4 c3 c2 c1 c0 command byte latched in at this point, and its contents will be acted on within 2 m s data valid in this time period note: sclk normally high (polarity = 1), phase = 1 dlc spi transfer 2
MC68HC58 data link controller operation motorola technical data 4-11 figure 4-8 host/dlc serial mode initialization routine 4.2.3 interrupt requests generation of interrupt requests is determined by the values of the configuration byte imsk and imod bits. by default, the dlc automatically asserts the int signal when one or more of four conditions occur. setting the imsk bit disables interrupts. setting the imod bit adds a fifth interrupt request condition. start dlc serial mode init routine dlc reset negated assert dlc cs load configuration byte into spi data register, initiating spi transfer is spi transfer complete? no retrieve the status byte received from the dlc from spi data register yes a a load ?oad as configuration byte immediate?command byte bit combination into spi data register, initiating spi transfer is spi transfer complete? no yes retrieve the data byte received from the dlc from spi data register and discard negate dlc cs dlc is now ready for j1850 multiplex bus communication end dlc serial mode init routine init flow
motorola data link controller operation MC68HC58 4-12 technical data when a condition that would normally cause an interrupt request occurs while the chip select input is asserted, the dlc cannot assert int until the logic level on the cs pin returns to one. in default configuration, the dlc asserts int under the following circumstances (a 4 mhz reference is assumed): ?when a frame completion code is placed in the rxfifo. the dlc asserts int within 10 m s of sensing eod on the j1850 bus. ?when the rxfifo buffer has 12 bytes in it and a 13th byte is received. the dlc asserts int within 15 m s after the trailing edge of the first bit of the 14th byte re- ceived. ?when the txfifo is half emptied during a block mode transmission (no byte in the txfifo buffer has been accompanied by a ?oad a last byte of transmit data command). six bytes remain to be transmitted when the interrupt request is made. the dlc asserts int within ten m s after the trailing edge of the last bit of the fifth byte transmitted. ?when the dlc comes out of standby mode due to activity on the sae j1850 bus. the dlc asserts int within 105 m s after the passive to active level of the sof symbol. ?after a configuration byte with imod set is sent to a dlc, the dlc also asserts int when a byte is received into an empty rxfifo. int assertion occurs 15 m s or less after the trailing edge of the first bit of the second byte received. the host mcu must use information in the status byte or the completion code to de- termine the interrupt source. it cannot deduce the cause of a txfifo half empty inter- rupt during block mode transmission because there is no explicit status indication for a txfifo buffer underrun. the host mcu can, however, monitor dlc status bytes for an indication that the txfifo buffer is no longer full. 4.3 transmitter operation the dlc transmitter drives the j1850 bus to at least 6.25 vdc, and expects the exter- nal load to pull the j1850 bus down below 1.5 vdc. the transmitter responds to feed- back from the receiver in order to determine precisely when to start and finish driving the bus. a set of basic transmit timing windows for j1850 bus symbols is stored in the dlc logic. the transmitter uses these timing windows as a basis for transmission, but if the receiver detects a change in the j1850 bus state during transmission, the trans- mitter switches to that state unless the switch causes the transmitter to lose arbitration. if arbitration is lost, the transmitter halts. this mechanism prevents j1850 bus conflict due to slight timing differences between j1850 bus nodes. only one frame appears on the j1850 bus during a transmission. symbols in the frame are driven and released by all participating nodes, but the end result is a single waveform. to transmit a frame on the j1850 bus, a host mcu first transfers frame data to the dlc. for parallel mode, a command byte need only accompany and identify the first and last byte(s). for serial mode, each byte of data must be accompanied by a command byte that tells the dlc whether the data is a first, intermediate, or last byte.
MC68HC58 data link controller operation motorola technical data 4-13 frames are sent in two basic modes: ?a complete frame is loaded into the txfifo buffer for transmission (normal mode). ?bytes of the frame are continuously loaded into the txfifo buffer as the message is being transmitted, until the entire frame has been sent (block mode). the dlc determines that a frame is completely loaded into the txfifo by reading a ?oad as last byte of transmit data?command byte. if no such command byte has been received, the transmitter operates in block mode until the command is received. the host mcu can monitor transmitter activity by polling individual status bytes, or servic- ing can be interrupt driven. refer to 4.5 block mode operation for more information. the transmitter waits until either an entire frame is in the txfifo buffer, or until the txfifo buffer is full before beginning a transmission. this prevents a data underrun during transmission of the first frame byte. once the j1850 bus is determined to be idle, transmission and j1850 bus arbitration begin. when a complete frame is in the txfifo buffer, the dlc status byte will indicate that the txfifo buffer is full until the transmission is successfully completed. a dlc automatically attempts to retransmit a frame if it loses arbitration or if errors are detected during transmission. the completion code placed in the rxfifo indicates to the host mcu when a frame has lost arbitration. the host mcu can terminate this automatic retry by writing a ?erminate automatic re- try ?(tar) command byte to the dlc. when the dlc receives the tar command, it completes any current transmission, then clears the txfifo buffer. if no transmission is in progress, and the txfifo buffer is full, the dlc attempts to transmit the frame in the txfifo buffer once, then clears the txfifo buffer. since a frame remains in the txfifo buffer until it is successfully transmitted, a host must clear the txfifo buffer if another frame is to be substituted for it. there are several commands that can accomplish this. refer to section 5 control and status codes for more information. one of these commands and the command to load the first byte of a new frame can be combined into a single byte that accompanies the first byte of new data. when a txfifo underrun occurs, the crc is intentionally corrupted by being comple- mented and appended to the transmission. figures 4-9 and 4-10 outline the basic software requirements for transferring data to the dlc in serial mode for transmission onto the j1850 multiplex bus. note particular applications may require more extensive error monitoring and handling routines than this flowchart displays. conditions reflect- ed in the retrieved status byte (received data bytes or j1850 bus sta- tus) are also not addressed.
motorola data link controller operation MC68HC58 4-14 technical data figure 4-9 host/dlc serial mode transmit routine (part 1 of 2) start tx data routine load first byte of message to is spi transfer complete? no retrieve the status byte received from the dlc from spi data register yes a dlc host trans flow 1 b load ?oad as transmit data byte negate dlc cs assert dlc cs be transmitted into spi data register, initiating spi transfer no yes is tx fifo status correct? e load ?oad as first byte of transmit data?command byte bit combination into spi data register, initiating spi transfer a is spi transfer complete? yes retrieve the data byte received from the dlc from spi data register and discard negate dlc cs minimum 2.5 m s delay between retrieve the status byte received from the dlc from spi data register no negation and assertion of cs load next byte of message to be transmitted into spi data register, initiating spi transfer is spi transfer complete? no yes b no yes is tx fifo status correct? e command byte bit combination into spi data register, initiating spi transfer is spi transfer complete? no yes one byte left in message? c no yes assert dlc cs
MC68HC58 data link controller operation motorola technical data 4-15 figure 4-10 host/dlc serial mode transmit routine (part 2 of 2) end tx data routine assert dlc cs is spi transfer complete? no retrieve the status byte received from the dlc from spi data register yes d dlc host trans flow 2 determine reason for incorrect negate dlc cs yes no is tx fifo status correct? is spi transfer complete? no yes c minimum 2.5 m s delay between negation and assertion of cs load last byte of message to be transmitted into spi data register, initiating spi transfer d e load ?oad as last byte of transmit data?command byte bit combination into spi data register, initiating spi transfer negate dlc cs dlc tx fifo status abort transmission, if appropriate, once an idle bus condition is detected on the j1850 bus, the dlc will begin necessary bus access procedure in order to transmit message to reset dlc transmitter
motorola data link controller operation MC68HC58 4-16 technical data 4.4 receiver operation the dlc receiver continuously monitors the j1850 bus for voltage swings of 0.375 volts centered around 3.875 vdc. it converts these swings to full logic level transitions, which are then clocked through a digital filter into the receiver. duration of the filtered j1850 bus states are timed by the control logic and compared to a set of received symbol threshold windows. each j1850 bus state is translated into one of the symbols or is flagged as a timing error. the receiver considers the j1850 bus to be idle when it has been in the passive state for a predetermined time. once an sof symbol is detected, the receiver stores frame bytes as they are received in the rxfifo buffer until an eod symbol is detected, or until the rxfifo buffer is full. as each byte is received, the dlc status is updated to reflect the state of the rxfifo (the status is updated each clock cycle during the frame). when all frame bytes have been received, the receiver checks the crc, but does not place it in the rxfifo buffer. instead, it appends a completion code byte to the frame. the byte contains information about the frame. the dlc receiver performs two basic error detection functions during message transmission and reception. these two error detection mechanisms are: ?the digital input filter ?the receiver j1850 bus monitor the digital filter eliminates j1850 bus noise spikes and transition noise lasting less than the propagation delay through the j1850 transceiver. filter operation is best de- scribed as a logic-level detector and a 4-bit counter. the counter counts up when the j1850 bus is active (logic level one is detected), and counts down when the j1850 bus is passive (logic level zero is detected). if a full count (0 or 15) occurs, the j1850 bus state transition is considered to be valid, and the signal transition passes to the receiv- er. as a result, the filter introduces a receive time-delay of 15 to 16 times the internal clock period. with a 2 mhz clock, the clock period is 0.5 m s, so the filter time delay is approximately 8 m s. each dlc receives every frame on the j1850 bus, including those it transmits. at the end of each reception from the j1850 bus, the receiver places a completion code byte into the rxfifo immediately following that frame. this byte contains transmitter action codes, in-frame response codes, and error codes. when a dlc is transmitting, the completion code information applies to both the transmitter and receiver. completion code bytes are also placed in the rxfifo when errors are detected, but the host mcu must read and interpret the codes to determine the nature of the error. available error information includes receiver overrun, transmitter underrun, loss of arbitration, incor- rect crc, incomplete byte indication, and bit timing error. refer to section 5 con- trol and status codes for more information. a host mcu can monitor the receiver by polling status bytes, or servicing can be inter- rupt driven. when interrupts are enabled, an interrupt request can be generated by the receiver in the following circumstances:
MC68HC58 data link controller operation motorola technical data 4-17 ?when the rxfifo buffer has received 13 bytes. ?when a completion code is placed in the rxfifo buffer. ?when a byte has been received into an empty rxfifo buffer (optional). for the dlc, status bytes and received data are transferred to the host mcu in pairs. in serial mode, received data remains in the rxfifo buffer until the host mcu sends a ?lush byte?command (data reads and flush commands can be executed at the same time). in parallel mode, the host mcu first reads the status byte, and a subsequent data read automatically flushes the data byte from the rxfifo buffer. figures 4-11 and 4-12 outline the basic software requirements for retrieving data which the dlc in serial mode has received from the j1850 multiplex bus. note particular applications may require more extensive error monitoring and handling routines than this flowchart displays. conditions reflect- ed in the retrieved status byte (txfifo status or j1850 bus status) are also not addressed. message filtering must be accomplished by the software.
motorola data link controller operation MC68HC58 4-18 technical data figure 4-11 host/dlc serial mode receive routine (part 1 of 2) start rx data routine load dummy data byte into is spi transfer complete? no retrieve the status byte received from the dlc from spi data register yes a dlc host rec flow 1 a retrieve the data byte assert dlc cs yes no is completion code at load ?lush byte?command byte is spi transfer complete? no yes spi data register, initiating spi transfer c head of rx fifo? bit combination into spi data data register, initiating spi transfer negate dlc cs received from the dlc from spi data register and store in rx message ram buffer minimum 2.5 m s delay between negation and assertion of cs b does message pass software no yes message filter? d
MC68HC58 data link controller operation motorola technical data 4-19 figure 4-12 host/dlc serial mode receive routine (part 2 of 2) load ?lush byte?command byte dlc host rec flow 2 yes no does completion code discard message data c bit combination into spi data register, initiating spi transfer is spi transfer complete? no yes retrieve completion code from spi data register negate dlc cs indicate valid data? yes no does completion code b indicate more data? end rx data routine f d assert dlc cs load dummy data byte into spi data register, initiating spi transfer is spi transfer complete? no yes e assert dlc cs e load dummy data byte into spi data register, initiating spi transfer is spi transfer complete? no yes retrieve completion code negate dlc cs from spi data register f is spi transfer complete? no yes load ?lush message?command byte bit combination into spi data register, initiating spi transfer negate dlc cs minimum 2.5 m s delay between negation and assertion of cs is spi transfer complete? no yes load ?lush byte?command byte bit combination into spi data register, initiating spi transfer
motorola data link controller operation MC68HC58 4-20 technical data 4.5 block mode operation the dlc has the capability of transmitting and receiving message frames which ex- ceed the frame length specified by j1850. these ?lock mode?messages are typically used in a production or diagnostic environment, and not during normal operation. when operating in block mode, the dlc can transmit or receive message frames con- taining an unlimited number of data bytes. the design of the dlc receiver allows it to receive block mode frames into the rxfifo buffer in a manner identical to normal j1850 frames. as each data byte is received from the j1850 bus, it is placed in the rxfifo buffer. throughout reception of the block mode frame, the status byte indicates to the host mcu the status of the rxfifo buffer. also, if interrupts are enabled, the dlc generates a host mcu interrupt each time the number of data bytes in the rxfifo buffer exceeds 12. as long as the host mcu retrieves the received frame bytes quickly enough to prevent the rxfifo buffer from overflowing, the dlc continues to place received data bytes into the rxfifo buffer. once the eod symbol is received from the j1850 bus, the crc byte of the frame is verified, and the appropriate completion code is placed in the rxfifo buffer. following this, the status byte indicates that a complete message frame is in the rxfifo buffer, and a host mcu interrupt, if enabled, is generated. this indicates to the host mcu that the block mode message frame is complete. if the rxfifo buffer does overflow, any remaining bytes of the frame are lost, and a completion code is placed in the rxfifo buffer, indicating that an rxfifo buffer over- run occurred. the dlc can transmit a message frame in block mode by completely filling the txfifo buffer with data bytes in a manner identical to a normal transmission, except that no byte is accompanied by the ?oad as last byte of transmit data?command. once the txfifo buffer is completely filled with data bytes, it automatically disables the termi- nate auto retry feature and begins normal j1850 bus access procedures. as long as the host mcu continues to supply data bytes without latching a ?oad as last byte of transmit data?command, the dlc continues to transmit the bytes in the block mode frame. when the last data byte of the block mode frame is transferred to the dlc, it should be accompanied by the ?oad as last byte of transmit data?command. this in- dicates to the dlc that the end of the block mode frame has been reached. after the last data byte has been transmitted, the dlc appends the crc byte to the frame. after the complete frame has been transmitted, the status byte shows the txfifo buffer to be empty. when the transmitter is operating in block mode, the status byte indicates ?xfifo al- most full?when the first frame byte has been sent out onto the j1850 bus, and ?xfifo contains some data?when the second byte is sent. if a dlc is configured for interrupt operation, an interrupt of the host mcu is generated when the txfifo buffer becomes half empty. as the txfifo buffer is refilled, status bytes and the interrupt line reflect the changing state of the txfifo buffer. once the ?oad as last byte of transmit data command is latched, the status byte shows the txfifo buffer to be full until transmis- sion of the block mode message is completed.
MC68HC58 data link controller operation motorola technical data 4-21 if the ?oad as first byte of transmit data?command is latched while the txfifo buffer is full during a block mode transfer, the data byte is not loaded and is lost. if the ?oad as first and last byte of transmit data?command is latched while the txfifo buffer is full during a block mode transfer, the data byte is not loaded and is lost. 4.6 break operation a break symbol on the j1850 bus causes any frame currently on the j1850 bus to be corrupted. the host mcu may command a dlc to send a break symbol. the symbol starts as soon as the command byte is latched. when a dlc receiver (including any dlc that sends the symbol) detects break on the j1850 bus, it places a completion code in the rxfifo buffer which indicates that the break was detected. if interrupts are enabled, int is also asserted. if a frame is being transmitted when the break is detected, the transmitter halts. since a break symbol will cause all frames on the j1850 bus to be corrupted, if the dlc is attempting to transmit when the break is detected, it will attempt to retransmit once an idle bus condition is detected following the break, unless automatic retry is disabled. 4.7 in-frame response (ifr) the sae standard j1850 allows for an optional ifr. a frame on the j1850 bus is de- termined to be ready for response when an eod period has elapsed. if a reply to the frame is initiated before the eof period also elapses, it is designated as an ifr. ifr transmissions are subject to the same arbitration as regular frames, but automatic re- try is disabled during an ifr. if the host wishes to send an ifr, a ?end ifr on eod?command byte accompanies the first byte of an ifr. this command flushes the txfifo buffer and queues the ifr. when the dlc receiver detects an eod, the ifr is sent, provided the following con- ditions are met: ?there are no errors in the frame requiring response. ?the ifr is loaded into the txfifo buffer after the sof of the frame requiring re- sponse is recognized, but before eod is detected. ?the first byte of the ifr is accompanied by either a ?oad as first byte of transmit data?command or ?oad as first and last byte of transmit data?command. if these conditions are satisfied, the dlc begins ifr transmission when eod occurs. if there is no last byte in the txfifo buffer when transmission begins, transmission follows normal block-mode rules. when the ?end ifr on eod?command flushes the txfifo buffer, the host mcu must reload and resend frames that are in the txfifo buffer when an ifr is queued, even when an ifr is not loaded successfully or loses arbitration.
motorola data link controller operation MC68HC58 4-22 technical data the ifr bit in the completion code byte indicates whether the associated frame in the rxfifo buffer is an ifr. when an ifr has been sent, the rxfifo buffer contains the initial frame, with completion code, plus the ifr and its completion code. the host mcu must check the completion codes to determine that an ifr has been received. an ifr starts with a normalization (nb) bit. this bit signals whether the ifr was queued by a ?end ifr on eod without crc?command (nb = 0), or by a ?end ifr on eod with crc command?(nb = 1). the ?n-frame response?command (ifrc) bit in the completion code byte also indicates whether a crc byte is appended to the ifr. the host mcu must monitor the ifrc if error checking is to be used. due to zero-dom- inance, j1850 bus arbitration between an ifr without crc and an ifr with crc is won by an ifr without crc. note a dlc cannot transmit an ifr to a message it is transmitting. table 4-4 shows ifr error conditions. when errors are detected during an ifr, the ifr is terminated. a completion code indicating that the frame was an ifr and that an error occurred is placed in the rxfifo buffer. table 4-4 ifr error conditions condition action taken error in frame requiring response transmitter reset, txfifo buffer flushed (no ifr sent) ifr loses arbitration transmission halts, txfifo buffer flushed (no ifr sent) txfifo buffer underrun crc complemented on truncated ifr error in ifr during transmission transmission halts, transmitter reset, txfifo buffer flushed j1850 bus idle when ifr loaded transmitter reset, txfifo buffer flushed ifr loaded after eod transmitter reset, txfifo buffer flushed ifr loaded without first byte transmitter reset, txfifo buffer flushed ifr command, no data transmitter reset, txfifo buffer flushed
MC68HC58 control and status codes motorola technical data 5-1 section 5 control and status codes the host mcu and the dlc exchange control and status information through encoded fields in four types of bytes. the two byte types containing control information originate in the host mcu. com- mand bytes direct a dlc to take certain actions. configuration bytes determine dlc operating parameters. the two byte types containing status information originate in the dlc. status bytes convey information concerning dlc buffers and activity to the host mcu. completion code bytes convey information concerning j1850 bus arbitration, frame type, and errors. the following paragraphs discuss each type of control and status byte in detail. to use this section, the reader must be familiar with dlc operation and with the interface be- tween the host mcu and the dlc. refer to section 4 data link controller operation for more information on dlc operation. appendix c dlc regis- ters provides a quick reference to all dlc register bit field encodings. 5.1 command byte the values of the fields in a command byte direct the dlc to take specified actions concerning operating mode, configuration bytes, and the txfifo and rxfifo buffers. commands must be latched into the dlc before they are executed. 5.1.1 gcom[7:5] ?general command field the host mcu directs the dlc to take certain actions by sending it gcom command codes. table 5-1 is a summary of the general commands. detailed discussion of each command follows. cbr ?command byte register 7 6 5 4 3 2 1 0 gcom btad rfc reset: 0 0 0 0 0 0 0 0
motorola control and status codes MC68HC58 5-2 technical data 5.1.1.1 do nothing the ?o nothing?command indicates to the dlc that a general command should not be executed. 5.1.1.2 enter standby mode the ?nter standby mode?command causes the dlc to operate in low power con- sumption (standby) mode. if the j1850 bus is not idle when this command is latched, the dlc becomes inactive within 5 m s after the j1850 bus goes idle. if the j1850 bus is idle when this command is latched, the dlc goes into standby mode immediately. toggling the cs line after this command has been latched, but before the dlc has entered standby mode, clears the command. 5.1.1.3 send break symbol when the ?end break symbol?command is latched in, the dlc immediately sends a break symbol on the j1850 bus, regardless of current status of the transmitter. 5.1.1.4 send ifr on eod with crc the ?end ifr on eod with crc?command causes the dlc to clear the transmitter and the txfifo buffer, terminate automatic frame retry, and originate an ifr with a crc. this command must accompany a data byte, and the command btad field must indicate either ?oad as first byte of transmit data?or ?oad as first and last byte of trans- mit data? the subsequent bytes in the same ifr must not be accompanied by this command. if this command is latched after an eod has already occurred, the ifr is not transmit- ted, and is lost. when this occurs, the dlc status byte indicates that the txfifo buffer is empty, and the dlc does not terminate automatic retry. table 5-1 general command summary value description 000 do nothing 001 enter standby mode 010 send break symbol 011 send ifr on eod with crc 100 terminate automatic retry 101 send ifr on eod without crc 110 reserved 111 abort transmission
MC68HC58 control and status codes motorola technical data 5-3 if a frame is in progress on the j1850 bus (no eod has been detected) when this com- mand is latched, the dlc sends the ifr only if no receiver errors are detected. when receiver errors are detected, the ifr is not transmitted, and is lost. if this occurs, the dlc status byte indicates that the txfifo buffer is empty, and the dlc does not ter- minate automatic retry. if the dlc is transmitting when this command is latched, a timing error or an incom- plete byte error will occur. the txfifo buffer is flushed, and both the frame and the ifr are lost. when additional ifr bytes are required, they must be placed in the txfifo buffer rap- idly enough to prevent underrun. the second ifr byte must be loaded before the fall- ing edge of the normalization bit, and subsequent bytes must be loaded within 500 m s of each other. if a txfifo underrun occurs, it is flagged as an error, and the crc byte is complemented and appended to the ifr being transmitted. 5.1.1.5 terminate auto retry the ?erminate auto retry?command disables automatic retry. a dlc will normally at- tempt to retransmit a frame that loses arbitration unless it is sending an ifr or a block mode transmission. if this command is latched while a transmission is in progress, the dlc attempts to complete the frame. after the frame is successfully transmitted, or after it loses arbi- tration, automatic retry terminates and the txfifo buffer is flushed. if this command is latched while a complete frame that has lost arbitration is in the buffer awaiting retransmission, the dlc attempts to retransmit the frame once more. after the frame is sent, automatic retry terminates and the txfifo buffer is flushed. if this command is latched while a complete frame that has not been transmitted is in the buffer awaiting transmission, the dlc attempts to send the frame once, then au- tomatic retry terminates and the txfifo buffer is flushed. 5.1.1.6 send ifr on eod without crc the ?end ifr on eod without crc?command causes a dlc to clear the transmitter and txfifo buffer, terminate automatic frame retransmission, and originate an ifr with no crc. this command must accompany a data byte, and the command byte btad field must indicate either ?oad as first byte of transmit data?or ?oad as first and last byte of transmit data? the subsequent bytes in the same ifr must not be accom- panied by this command. if this command is latched while the j1850 bus is idle, or between eod and eof, the ifr is not transmitted, and is lost. when this occurs, the dlc status byte indicates that the txfifo buffer is empty, and the dlc does not terminate automatic retry.
motorola control and status codes MC68HC58 5-4 technical data if a frame is in progress on the j1850 bus (no eod has been detected) when this com- mand is latched, the dlc sends the ifr only if no receiver errors are detected. when receiver errors are detected, the ifr is not transmitted, and is lost. if this occurs, the dlc status byte indicates that the txfifo buffer is empty, and the dlc does not ter- minate automatic retry. if the dlc is transmitting when this command is latched, a timing error or an incom- plete byte error occurs. the txfifo buffer is flushed, and both the frame and the ifr are lost. when additional ifr bytes are required, they must be placed in the txfifo buffer rap- idly enough to prevent underrun. the second ifr byte must be loaded before the fall- ing edge of the normalization bit, and subsequent bytes must be loaded within 500 m s of each other. if a txfifo underrun occurs, it is flagged as an error. 5.1.1.7 abort transmission the ?bort transmission?command causes the transmitter to be reset immediately. any transmission in progress is terminated, and the txfifo buffer is flushed. the first byte of a new frame can accompany this command. 5.1.2 btad[4:2] ?byte type and destination field the btad field tells the dlc how to treat the data byte that accompanies a command byte. table 5-2 is a summary of byte type and destination commands. detailed dis- cussion of each command follows. 5.1.2.1 do not load the ?o not load?command indicates to the dlc that a byte type and destination com- mand should not be executed. 5.1.2.2 load as transmit data the ?oad as transmit data?command places an accompanying data byte in the txfifo buffer for transmission. table 5-2 byte type and destination summary value description 000 do not load 001 load as transmit data 010 reserved 011 load as last byte of transmit data 100 load as configuration byte 101 load as first byte of transmit data 110 load as configuration byte-immediate 111 load as first and last byte of transmit data
MC68HC58 control and status codes motorola technical data 5-5 if this command is latched while the txfifo buffer is full during a block mode transfer, the data byte is not loaded and is lost. if this command is latched while a previously loaded complete frame is being transmit- ted, or is in the txfifo buffer awaiting transmission, the data byte is not loaded and is lost. if this command is latched when the txfifo buffer is empty, the data byte is not load- ed and is lost. 5.1.2.3 load as last byte of transmit data the ?oad as last byte of transmit data?command indicates that the accompanying data byte is the last byte of a frame. after the byte is placed in the txfifo buffer for transmission, the txfifo status field (tmfs) in the status byte is configured to %11 (txfifo full). if this command is latched while a previously loaded complete frame is being transmit- ted, the accompanying data byte is discarded. if this command is latched when the txfifo buffer is empty, the accompanying data byte is discarded. 5.1.2.4 load as configuration byte the ?oad as configuration byte?command indicates that the accompanying data byte contains dlc configuration data. changes in configuration are performed after current j1850 bus activity is finished unless this command immediately follows reset. in this case, the dlc is configured at least 1.2 ms after the command is latched. 5.1.2.5 load as first byte of transmit data the ?oad as first byte of transmit data?command indicates that the accompanying data byte is the first byte of a frame. after the byte is placed in the txfifo buffer for transmission, the tmfs in the status byte is set to %01 (txfifo contains data byte). if the transmitter encounters another ?irst byte?command in the buffer before decod- ing a valid ?ast byte?command, it sends a complemented crc and halts. a comple- tion code with the error flag (errf) bit set and a transmitter status (tms) field value of %10 (transmitter underrun) is placed in the rxfifo buffer. the second ?irst byte command and any succeeding bytes are not transmitted. if this command is latched while a previously loaded complete frame is being transmit- ted, the data byte is not loaded and is lost. 5.1.2.6 load as configuration byte ?immediate the ?oad as configuration byte ?immediate?command indicates that the accompany- ing data byte contains dlc configuration data. changes in configuration are per- formed immediately. this command should only be used for system initialization and test.
motorola control and status codes MC68HC58 5-6 technical data 5.1.2.7 load as first and last byte of frame the ?oad as first and last byte of frame?command indicates that the accompanying data byte is a one byte frame. after the byte is placed in the txfifo buffer for trans- mission, the tmfs in the status byte is set to %11 (txfifo full). if this command is latched while a previously loaded complete frame is in the buffer awaiting transmission, the accompanying data byte will be discarded. if this command is latched while a previously loaded complete frame is being transmit- ted, the accompanying data byte will be discarded. 5.1.3 rfc[1:0] ?receive fifo command field table 5-3 displays the rxfifo commands. 5.1.3.1 do nothing the ?o nothing?command indicates to the dlc that an rxfifo buffer command should not be executed. 5.1.3.2 flush byte the ?lush byte?command flushes the first data byte or completion code in the rxfifo buffer. ?lush byte?commands cannot be queued. when there is nothing in the buffer, no action is taken if a byte arrives after the command is latched. this is the only com- mand that can flush a completion code. 5.1.3.3 flush frame the ?lush frame?command flushes the current frame except for the completion code generated when the frame has been completely received. if interrupts are enabled when a ?lush frame?command is executed, the receiver will only generate an interrupt request once the completion code is at the head of the rxfifo. when the rxfifo buffer is flushed, it is not completely cleared, but cycled until the first byte in the rxfifo buffer is a completion code. if the command is latched when a complete frame is in the buffer, the entire frame, ex- cept for the completion code, is flushed. if the command is latched when there is nothing in the buffer, the next frame, except for the completion code, is flushed. table 5-3 rfc field encoding value description 00 do nothing 01 reserved 10 flush byte or completion code 11 flush frame except for completion code
MC68HC58 control and status codes motorola technical data 5-7 if the command is latched while a frame is being received, all bytes in the rxfifo buff- er and all subsequent bytes received before the completion code is generated, are flushed. in the two previous instances, the rxfifo status (rfs) field in the status byte may be invalid until the completion code is recognized. if the command is latched while the first byte in the rxfifo buffer is a completion code, the rxfifo buffer is not flushed. 5.2 configuration byte the fields in the configuration byte determine the basic operational parameters of the dlc. a host mcu cannot read configuration information from the dlc. once a configuration byte is sent to the dlc, operating parameters cannot change until a new byte is sent, or a reset occurs. 5.2.1 tm ?test mode control bit setting the tm bit enables the receive data disable test mode. this mode is used for motorola internal testing only. 0 = normal operation 1 = test mode 5.2.2 tc[6:5] ?test configuration field the tc bit field selects one of four operating modes. when tc value is %00 (default), the dlc operates normally. each of the other values selects a test mode. these modes are used for motorola internal testing only. 5.2.3 imsk ?interrupt mask bit the imsk bit determines dlc interrupt request capability. when interrupts are dis- abled, the dlc cannot exit standby mode upon detection of j1850 bus activity. 0 = all interrupts to the mcu are enabled 1 = all interrupts to the mcu are disabled cbr ?configuration byte register 7 6 5 4 3 2 1 0 tm tc imsk imod oscd 4x reset: 0 0 0 0 0 1 1 0
motorola control and status codes MC68HC58 5-8 technical data 5.2.4 imod ?interrupt mode bit the imod bit controls an additional interrupt source to the default interrupt sources. when imod is set, an interrupt request is made when a data byte is received into an empty rxfifo buffer. subsequent bytes do not cause an interrupt request unless the rxfifo is emptied before they are received. 0 = default interrupts are the only ones enabled 1 = additional interrupt source added to default sources 5.2.5 oscd[2:1] ?oscillator divisor field the oscd bit field determines dlc internal clock frequency. the dlc internal clock frequency is derived from a combination of the external clock frequency and the oscd value. table 5-4 shows frequency division factors and the internal clock frequency with various references. a 2 mhz internal clock frequency is required for normal oper- ation. 5.2.6 4x ?high-speed control bit setting this bit places the dlc in high-speed data transfer mode. j1850 bus wave- shaping is disabled. 0 = normal clock division 1 = four times normal clock speed 5.3 status byte the status byte register conveys information about data and shows the condition of the dlc at the time of receipt. results of commands that are in progress may not be reflected in the status byte until the command is completely executed. for a dlc operating in parallel mode, the host mcu can read the status byte alone, and a subsequent data read automatically flushes the data byte from the buffer. for a dlc operating in spi mode, status bytes and received data are transferred to the host mcu in pairs. when the host reads received data, it remains in the rxfifo buffer until a flush command is given. the flush command can accompany the read command. the dlc does not report the status of an action caused by the current transfer. table 5-4 internal clock frequency derivations oscd clock external clock value divisor 2 mhz 4 mhz 6 mhz 8 mhz 00 1 2 mhz 4 mhz 6 mhz 8 mhz 01 2 1 mhz 2 mhz 3 mhz 4 mhz 10 3 0.66 mhz 1.33 mhz 2 mhz 2.66 mhz 11 4 500 khz 1 mhz 1.5 mhz 2 mhz
MC68HC58 control and status codes motorola technical data 5-9 all information in the status byte is frozen while cs is asserted, and updated when cs is negated. 5.3.1 rfs[7:5] ?receive fifo status field this bit field shows the status of the rxfifo buffer. when interrupts are enabled, rfs can be used to determine the source of an interrupt request. table 5-5 shows the rxfifo status encoding field. in the dlc, when the rfs bit field indicates that a com- pletion code is at the head of the buffer, the accompanying data byte contains that same completion code. 5.3.1.1 buffer invalid or empty this value indicates that the accompanying data byte is not valid because the rxfifo buffer is empty or a flush frame command is being executed. 5.3.1.2 buffer contains more than one byte this value indicates that the rxfifo buffer contains two to 12 bytes of data and no completion code. 5.3.1.3 buffer contains a completion code this value indicates that the rxfifo buffer contains both data bytes and a completion code. the completion code is not at the head of the buffer. 5.3.1.4 thirteenth byte received this value indicates that the rxfifo buffer contains 12 bytes and a 13th byte has been received. there is no completion code in the buffer. sbr ?status byte register 7 6 5 4 3 2 1 0 rfs dli netf 4xmd tmfs reset: 0 0 0 x 0 0 0 0 table 5-5 rfs field encoding value description 000 buffer invalid or empty 001 buffer contains more than one byte 010 buffer contains a completion code 011 data byte in 13th buffer position, no completion code 100 one data byte in buffer 101 completion code at head of buffer, more bytes available 110 completion code at head of buffer, another frame available 111 completion code only at head of buffer
motorola control and status codes MC68HC58 5-10 technical data 5.3.1.5 one byte in buffer this value indicates that the rxfifo buffer contains one byte that is not a completion code. 5.3.1.6 completion code at head of buffer, more bytes available this value indicates that there is a completion code at the head of the rxfifo buffer, and additional bytes but no additional completion codes are in the buffer. 5.3.1.7 completion code at head of buffer, frame available this value indicates that there is a completion code at the head of the rxfifo buffer, and additional bytes and an additional completion code are in the buffer. 5.3.1.8 completion code only at head of buffer this value indicates that there is a completion code at the head of the rxfifo buffer, and no additional bytes are in the buffer. indication usually occurs after execution of a flush frame command. 5.3.2 dli ?data link idle bit dli is set when the j1850 bus is idle. dli is cleared when the j1850 bus has been active for longer than the digital filter time constant, or when an eod symbol is being timed by the receive logic. once cleared, dli does not go to logic level one until an eod symbol has been received. if the j1850 bus remains active for longer than the minimum break symbol definition, a completion code indicating a break has oc- curred is placed in the rxfifo buffer. a prolonged data link active indication may in- dicate that the j1850 bus is shorted to 12 vdc. 0 = sae j1850 bus is active 1 = sae j1850 bus is idle 5.3.3 netf ?network fault bit this value indicates the dlc j1850 bus connection is shorted to ground. when a hard- ware fault prevents the dlc receiver from sensing an active state after the transmitter has driven the j1850 bus for 60 m s, netf is set. after netf is set, only an abort transmission command or assertion of the dlc rst input can restart the dlc. when the short is momentary, it is appropriate to try reloading and retransmission. however, if the problem is a defective receiver, retransmission could corrupt another frame. 0 = active state occurred before 60 m s 1 = active state not sensed after 60 m s
MC68HC58 control and status codes motorola technical data 5-11 5.3.4 4xmd ?4x mode bit this value indicates the dlc is operating in high-speed mode without waveshaping. this mode is not used during normal operation. 0 = dlc operating in normal mode 1 = dlc operating at 41.67 kbps 5.3.5 tmfs[1:0] ?txfifo status field this bit field shows the status of txfifo buffer. table 5-6 shows the txfifo status encoding field. 5.3.5.1 buffer empty this value indicates there are no data bytes in txfifo buffer. 5.3.5.2 buffer contains data this value indicates that the txfifo buffer contains one to nine bytes of data. 5.3.5.3 buffer almost full this value indicates that the txfifo buffer contains ten bytes of data. 5.3.5.4 buffer full this value indicates that either the txfifo buffer contains 11 bytes of data (in block transmission mode), or that it contains a byte that was accompanied by a ?ast byte command. 5.4 completion code byte when a frame is complete, after the time period for an eod symbol has elapsed, the dlc generates a completion code byte and transfers it to the host mcu in the same way that a received data byte is transferred. the accompanying status byte indicates that it is a completion code byte. the completion code byte contains an error flag, transmitter action codes, ifr codes, and error codes. when a dlc is transmitting, completion code information applies to both transmitter and receiver. any activity on the j1850 bus longer than the digital filter time constant causes a com- pletion code byte to be placed in the rxfifo buffer after the j1850 bus is idle for an eod length of time. table 5-6 tmfs field encoding value description 00 buffer empty 01 buffer contains data bytes 10 buffer almost full 11 buffer full
motorola control and status codes MC68HC58 5-12 technical data 5.4.1 errf ?error bit this bit indicates whether the receiver detected an error during the frame. when errf is set, the errc field indicates which error occurred. 0 = no error occurred 1 = error occurred 5.4.2 rfo ?receive fifo overrun bit when the rfo bit is set, a rxfifo buffer overrun has occurred. this means that the host mcu has not read the rxfifo buffer regularly enough to prevent incoming frame bytes from being lost. rfo is set when the first bit of the 21st data byte is received. previously received data bytes remain in the buffer. when rfo is set, no other com- pletion code bits can be considered valid. there is no way to detect break when the buffer has overflowed. 0 = no receiver buffer overrun occurred 1 = receiver buffer overrun occurred 5.4.3 tms[5:4] ?transmitter status field this bit field shows transmitter status during the frame just received. table 5-7 shows transmitter status field encoding. 5.4.3.1 transmitter not involved this value indicates that the transmitter did not perform j1850 bus contention for this frame. frame did not originate from this node. 5.4.3.2 transmitter underrun this value indicates that a frame was transmitted but was not completed. this is not an indication that the transmission lost j1850 bus contention. ccbr ?completion code byte register 7 6 5 4 3 2 1 0 errf rfo tms ifr ifrc errc reset 0 0 0 0 0 0 0 0 table 5-7 tms field encoding value description 00 transmitter not involved 01 transmitter underrun 10 transmitter lost arbitration 11 transmitter successful
MC68HC58 control and status codes motorola technical data 5-13 5.4.3.3 transmitter lost arbitration this value indicates that the transmitter lost contention, or an rxfifo buffer overrun occurred. if overrun occurred, transmitter may not have been arbitrated against, and transmission may not have stopped. 5.4.3.4 transmitter successful this value indicates that a frame transmitted successfully. frame originated from this node. 5.4.4 ifr ?in-frame response bit this bit indicates whether or not a frame is an ifr. 0 = not an ifr 1 = ifr 5.4.5 ifrc ?in-frame response crc bit this bit indicates whether or not an ifr has an appended cyclic redundancy check. 0 = ifr without crc 1 = ifr with crc 5.4.6 errc[1:0] ?error code field this bit field is used in conjunction with the error flag. it indicates which errors were detected. errors are reported in precedence order; the higher the errc value, the higher the priority. if any of these error conditions are detected, a pending eod re- sponse frame (ifr) is not sent. table 5-8 shows the errc encoding field. 5.4.6.1 crc error this value indicates that the cyclic redundancy check is incorrect or that a receiver overrun has occurred. 5.4.6.2 incomplete byte error this value indicates that an incorrect modulus eight count occurred during reception of this frame, and that an incomplete byte was received. table 5-8 errc field encoding value description 00 crc error 01 incomplete byte 10 bit timing error 11 break
motorola control and status codes MC68HC58 5-14 technical data 5.4.6.3 bit timing error this value indicates that a bit in the received frame did not match the timing window stored in the control logic. the receiver immediately places a completion code byte in the buffer upon detection of this error. this generally occurs as a result of mismatched clock divisors between nodes, but may occur if a break is detected after the j1850 bus has been passive for 8 to 34 m s. when this occurs, two completion codes (a bit error and a break) are generated. 5.4.6.4 break error this value indicates that a break symbol was detected on the j1850 bus, or the j1850 bus was shorted high for longer than the defined break period, and has re- covered.
MC68HC58 electrical characteristics motorola technical data a-1 appendix a electrical characteristics notes: 1. measured with no activity on the host /dlc interface lines. table a-1 operating conditions symbol definition conditions min typ max units v batt voltage at battery pin during transmit operation rs = 20 w max. (protection circuit) 7.0 12.0 26.5 v voltage at battery pin during receive operation rs = 20 w max. (protection circuit) 4.9 12.0 26.5 v v cc , v dd transceiver, logic supplies 4.75 5.0 5.25 v pc max maximum continuous power dissipation 7.8 khz bus waveform (50% duty cycle); 4.00 mhz resonator; 16-volt battery 333 mw i batt , standby battery standby current dlc in standby mode 3 5 m a i batt , draw battery current draw 7.8 khz bus waveform (50% duty cycle); 4.00 mhz resonator; 16-volt battery 3.5 50 ma i dd , draw logic current draw 100% bus utilization 4.00 mhz resonator 1.5 4 ma i dd , draw, slp 1 logic current draw, standby mode dlc in sleep mode 3 5 m a i cc , draw transceiver current draw 100% bus utilization 4.00 mhz resonator 0.3 1 ma i cc , draw, slp transceiver current draw, standby mode dlc in sleep mode 40 55 m a i psen , source psen pin max source v batt = 9 v rseries = 33 k w 10 500 m a i olpsen psen leakage standby mode, power supply off ? 5 m a v psen psen pin output voltage v batt = 9 v rseries = 33 k w 8.3 v v lh input range on all logic pins ?.5 5.75 v t st storage temperature range ?5 150 c t j maximum junction tem- perature 150 c t a operating temperature range ?0 125 c i bat , sleep battery sleep current dlc in sleep mode 5 ma
motorola electrical characteristics MC68HC58 a-2 technical data notes: 1. interrupt request line is an open drain output; therefore, v oh is not applicable. table a-2 electrical characteristics symbol description conditions min max units v oh 1 minimum guaranteed out- put high voltage i oh = ?00 m a v dd 0.8v ? v ol maximum guaranteed output low voltage i ol = 1.6 ma 0.4 v v ih minimum guaranteed in- put high voltage i in = 10 m a v dd x 0.7v ? v il maximum guaranteed in- put low voltage i in = 10 m a 0.8 v i in (except osc1, cs ) input current limits ?0 10 m a i ih, osc1 maximum guaranteed in- put high current v dd = 4.75 to 5.25 v 0.525 10.50 m a i il, osc1 maximum guaranteed in- put low current v dd = 4.75 to 5.25 v ?0.50 ?.525 m a i in cs chip select input current limit ?50 50 m a i oz (except osc1) output leakage high-z v out to gnd ?0 10 m a c i digital input capacitance 8 pf c io digital input/output capacitance 10 pf c load maximum load capacitance 100 pf table a-3 absolute maximum ratings symbol description min max units v batt supply voltage 0.5 26.5 v v batt supply voltage (t 1 ms) 40.0 v v cc ,v dd supply voltage 0.5 5.75 v t stg storage temperature range ?5 +150.0 c t j maximum junction temperature +150.0 c
MC68HC58 electrical characteristics motorola technical data a-3 figure a-1 parallel interface timing eclk addr0 t cyc t r t f t weh t wel t assu t ash t cssu cs t csh t csdb t csst r/w t rwsu t rwh data in t dsui t dhi data out t dvo t dho t dho dlc par int tim
motorola electrical characteristics MC68HC58 a-4 technical data notes: 1. within double-byte reads and writes. 2. between successive commands; also between consecutive ?uto-finishes?of data in dlc parallel mode. 3. needed between successive status byte reads to properly update status. table a-4 parallel interface parameters symbol description pin min max units t cyc e-clock cycle time ec 238 ns t wel e-clock pulse width low ec 105 ns t weh e-clock pulse width high ec 100 ns t r,f e-clock rise and fall time ec 0 20 ns t assu address select setup time a0 20 ns t ash address select hold time a0 20 ns t cssu chip-select setup time cs 5ns t csh chip-select hold time cs 5ns t csdb chip-select double 1 cs 060ns t csst chip-select status time 2, 3 cs 3 m s t rwsu r/w setup time r/w 25 ns t rwh r/w hold time r/w 20 ns t dsui data in setup time d0?7 45 ns t dhi data in hold time d0?7 15 ns t dvo data out valid time d0?7 75 ns t dho data out hold time d0?7 5 ns t dto data out three-state time d0?7 40 ns
MC68HC58 electrical characteristics motorola technical data a-5 figure a-2 spi timing ?active high sclk figure a-3 spi timing ?active low sclk cs sclk somi simo t lead note: sclk normally low t acc t skhi t sklo t rise t cyc t fall t lag t cs t ho t hold t setup t pdo t dis dlc spi-hsclk tim note: sclk normally high simo somi sclk cs t acc t setup t hold t pdo t rise t dis t fall t slag t lead t skhi t sklo t ho t cs t cyc t hold dlc spi-lsclk tim
motorola electrical characteristics MC68HC58 a-6 technical data notes: 1. maximum spi frequency is 4.2 mhz. table a-5 serial interface parameters symbol description min max units t cs minimum time between consecutive cs assertions 3.0 m s t cyc minimum sck cycle time 1 238 ns t skhi minimum clock high time 80 ns t sklo minimum clock low time 80 ns t lead minimum enable lead time 100 ns t lag minimum enable lag time 100 ns t acc access time 60 ns t pdo maximum data out delay time 59 ns t ho minimum data out hold time 0 ns t dis maximum data out disable time 240 ns t setup minimum data setup time 30 ns t hold minimum data hold time 30 ns t rise maximum time for input to go from v ol to v oh ?5ns t fall maximum time for input to go from v oh to v ol ?5ns t slag minimum time after data hold time that cs may be negated 100 ns
MC68HC58 electrical characteristics motorola technical data a-7 figure a-4 dlc interrupt timing message on bus configuration byte interrupt mode bit = 0 t acint dlc inactive, beginning of first message interrupt requested t eodint message on bus configuration byte interrupt mode bit = 0 interrupt requested eod sensed t 13int message on bus configuration byte interrupt mode bit = 0 interrupt requested 13th byte received t txint transmitting message on bus configuration byte interrupt mode bit = 0 interrupt requested 6 bytes left to transmit t bint transmitting message on bus configuration byte interrupt mode bit = 1 interrupt requested first byte transmitted dlc int tim
motorola electrical characteristics MC68HC58 a-8 technical data figure a-5 reset timing table a-6 standby and interrupt timing symbol description min max units t acdly period from detection of bus activity until assertion of psen, or period from application of 5 vdc until assertion of psen ? m s t acint period from detection of bus activity by a dlc in standby condition until int assertion 105 m s t eodint period from detection of eod on the bus until int assertion ? m s t 13int period from receipt of 13th byte until int assertion 5 m s t txint period from when there are six bytes left to transmit until int assertion ? m s t bint period from receipt of first byte until int assertion 5 m s command configuration v batt v cc , v dd rst host 12v 0v 5v 0v 5v 0v rst t rst initialization command and configuration latched t vsim t vsu t con dlc reset timing 1
MC68HC58 electrical characteristics motorola technical data a-9 figure a-6 variable pulse-width modulation (vpw) symbol timings table a-7 reset timing symbol description min max units t vsim v dd , v ss simultaneous switch delay 6 10 ms t vsu v dd , v ss set up time 50 100 ms t con immediate configuration time 300 1200 m s t rst reset pulse width 1 m s 13 11 10 12 16 14 sof 15 18 ? ? ? ? eod brk ? eof 17 ifs vpwm tim
motorola electrical characteristics MC68HC58 a-10 technical data notes: 1. the receiver symbol timing boundaries are subject to an uncertainty of 1 m s due to sampling considerations. table a-8 transceiver requirements (dc) symbol description conditions min max units v oh guaranteed output high voltage 100% bus utilization, 4 mhz (v batt = 9 to 26.5v) 6.25 8.0 v 100% bus utilization, 4 mhz (v batt = 7 to 9v) 5.25 8.0 v ol, max maximum guaranteed output low voltage 100% bus utilization, 4 mhz 1.5 v v il, max maximum input low voltage v cc = 4.75 to 5.25 v 3.5 v v ih, min minimum input high voltage v cc = 4.75 to 5.25 v 4.25 v v t nominal receiver trip point 3.875 v table a-9 transmitter vpw symbol timings (v batt = 12v, v cc = 5.0v, v ss = 0v, t a = 25 c, unless otherwise noted.) characteristic number symbol min typical max unit passive logic 0 10 t tvp1 58.0 64.0 70.0 m s passive logic 1 11 t tvp2 122.0 128.0 134.0 m s active logic 0 12 t tva1 122.0 128.0 134.0 m s active logic 1 13 t tva2 58.0 64.0 70.0 m s start of frame (sof) 14 t tva3 193.0 200.00 207.0 m s end of data (eod) 15 t tvp3 193.0 200.0 207.0 m s end of frame 16 t tv4 271.0 280.0 289.0 m s inter-frame separator (ifs) 17 t tv6 300.0 m s break (brk) 18 t tv7 1200 m s table a-10 receiver vpw symbol timings (v batt = 12v, v cc = 5.0v, v ss = 0v, t a = 25 c, unless otherwise noted.) characteristic number symbol 1 min typical max unit passive logic 0 10 t rvp1 34.0 64.0 96.0 m s passive logic 1 11 t rvp2 96.0 128.0 163.0 m s active logic 0 12 t rva1 96.0 128.0 163.0 m s active logic 1 13 t rva2 34.0 64.0 96.0 m s start of frame (sof) 14 t rva3 163.0 200.0 239.0 m s end of data (eod) 15 t rvp3 163.0 200.0 239.0 m s end of frame 16 t rv4 239.0 280.0 320.0 m s break 18 t rv7 768.0 m s
MC68HC58 mechanical data and ordering information motorola technical data b-1 appendix b mechanical data and ordering information the MC68HC58 is available in two package options, a 28-pin plcc (plastic leaded chip carrier) and a 28-pin soic (small outline integrated circuit). refer to figures b- 1 and b-2 . figures b-3 and b-4 show the corresponding dimensional drawings. ordering information is available in table b-1 . b.1 pin assignments figure b-1 MC68HC58 28-pin plcc dlc (top view) v cc psen v batt bus load v ssd data0 rst cs *(sclk)/eclk *(simo)/addr0 *(somi)/r/w int v dd * ( ) indicates pin assignments for serial mode operation data7 data6 data5 data4 data3 data2 data1 osc1 osc2 loti v ssa lito prlmd rext dlc pin assignment
motorola mechanical data and ordering information MC68HC58 b-2 technical data figure b-2 MC68HC58 28-pin soic dlcp 28-pin soic *(somi)/r/w int v dd data7 data6 data5 9 10 11 12 13 14 *(simo)/addr0 8 *(sclk)/eclk 7 cs 6 rst 5 osc1 4 osc2 3 loti 2 v ssa 1 data1 data2 data3 data4 18 17 16 15 data0 19 v ssd 20 load 21 bus 22 v batt 23 p sen 24 v cc 25 rext 26 prlmd 27 lito 28 * ( ) indicates pin assignments for serial mode operation
MC68HC58 mechanical data and ordering information motorola technical data b-3 5.5 package dimensions figure b-3 case outline #776-02 notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dimension g1, true position to be measured at datum t, seating plane. 3. dimensions r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). n m l v w d d y brk 28 1 view s s lm s 0.010 (0.250) n s t s lm m 0.007 (0.180) n s t 0.004 (0.100) g1 g j c z r e a seating plane s lm m 0.007 (0.180) n s t t b s lm s 0.010 (0.250) n s t s lm m 0.007 (0.180) n s t u s lm m 0.007 (0.180) n s t z g1 x view dd s lm m 0.007 (0.180) n s t k1 view s h k f s lm m 0.007 (0.180) n s t dim min max min max millimeters inches a 0.485 0.495 12.32 12.57 b 0.485 0.495 12.32 12.57 c 0.165 0.180 4.20 4.57 e 0.090 0.110 2.29 2.79 f 0.013 0.019 0.33 0.48 g 0.050 bsc 1.27 bsc h 0.026 0.032 0.66 0.81 j 0.020 0.51 k 0.025 0.64 r 0.450 0.456 11.43 11.58 u 0.450 0.456 11.43 11.58 v 0.042 0.048 1.07 1.21 w 0.042 0.048 1.07 1.21 x 0.042 0.056 1.07 1.42 y 0.020 0.50 z 2 10 2 10 g1 0.410 0.430 10.42 10.92 k1 0.040 1.02
motorola mechanical data and ordering information MC68HC58 b-4 technical data figure b-4 case outline #751f-04 b.2 obtaining updated MC68HC58 mechanical information although all devices manufactured by motorola conform to current jedec standards, complete mechanical information regarding MC68HC58 data link controller is available through motorola? design-net. to download updated package specifications, perform the following steps: 1. visit the design-net case outline database search engine at http://design-net.com/cgi-bin/cases. 2. enter the case outline number, located in figures b-3 and b-4 without the revision code (for example, 864a, not 864a-03) in the field next to the search button. 3. download the file with the new package diagram. b.3 ordering information table b-1 MC68HC58 ordering information mc order information package description MC68HC58 776-02 28-pin plcc 751f -04 28-pin soic notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. j k f 1 15 14 28 a b 28x 14x d p s a m 0.010 (0.25) b s t m 0.010 (0.25) b m 26x g t seating plane c x 45 r m dim min max min max inches millimeters a 17.80 18.05 0.701 0.711 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.41 0.90 0.016 0.035 g 1.27 bsc 0.050 bsc j 0.23 0.32 0.009 0.013 k 0.13 0.29 0.005 0.011 m 0 8 0 8 p 10.01 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029
MC68HC58 dlc registers motorola technical data c-1 appendix c dlc registers c.1 command byte register cbr ?command byte register 7 6 5 4 3 2 1 0 gcom btad rfc reset: 0 0 0 0 0 0 0 0 table c-1 general command summary (gcom) value description 000 do nothing 001 enter standby mode 010 send break symbol 011 send ifr on eod with crc 100 terminate automatic retry 101 send ifr on eod without crc 110 reserved 111 abort transmission table c-2 byte type and destination summary (btad) value description 000 do not load 001 load as transmit data 010 reserved 011 load as last byte of transmit data 100 load as configuration byte 101 load as first byte of transmit data 110 load as configuration byte-immediate 111 load as first and last byte of transmit data table c-3 rfc field encoding (rfc) value description 00 do nothing 01 reserved 10 flush byte 11 flush frame except for completion code
motorola dlc registers MC68HC58 c-2 technical data c.2 configuration byte register cbr ?configuration byte register 7 6 5 4 3 2 1 0 tm tc imsk imod oscd 4x reset: 0 0 0 0 0 1 1 0 table c-4 test mode control bit (tm) value description 0 normal operation 1 test mode table c-5 test configuration field (tc) value description 00 normal mode factory test table c-6 interrupt mask bit (imsk) value description 0 all interrupts to the mcu are enabled 1 all interrupts to the mcu are disabled table c-7 interrupt mode bit (imod) value description 0 default interrupts are the only ones enabled 1 additional interrupt source added to default sources table c-8 internal clock frequency field (oscd) oscd clock external clock value divisor 2 mhz 4 mhz 6 mhz 8 mhz 00 1 2 mhz 4 mhz 6 mhz 8 mhz 01 2 1 mhz 2 mhz 3 mhz 4 mhz 10 3 0.66 mhz 1.33 mhz 2 mhz 2.66 mhz 11 4 500 khz 1 mhz 1.5 mhz 2 mhz table c-9 high-speed control bit (4x) value description 0 normal clock division 1 4 times normal clock speed
MC68HC58 dlc registers motorola technical data c-3 c.3 status byte register sbr ? status byte register 7 6 5 4 3 2 1 0 rfs dli netf 4xmd tmfs reset: 0 0 0 x 0 0 0 0 table c-10 receive fifo status field encoding (rfs) value description 000 buffer invalid or empty 001 buffer contains more than one byte 010 buffer contains a completion code 011 data byte in 13th buffer position, no completion code 100 one data byte in buffer 101 completion code at head of buffer, more bytes available 110 completion code at head of buffer, another frame available 111 completion code only at head of buffer table c-11 data link idle bit (dli) value description 0 sae j1850 bus is active 1 sae j1850 bus is idle table c-12 network fault bit (netf) value description 0 active state occurred before 60 m s 1 active state not sensed after 60 m s table c-13 4x mode bit (4xmd) value description 0 dlcp/s operating in normal mode 1 dlcp/s operating at 41.67 kbps table c-14 transmit fifo status field encoding (tmfs) value description 00 buffer empty 01 buffer contains data bytes 10 buffer almost full 11 buffer full
motorola dlc registers MC68HC58 c-4 technical data c.4 completion code byte register ccbr ?completion code byte register 7 6 5 4 3 2 1 0 errf rfo tms ifr ifrc errc reset 0 0 0 0 0 0 0 0 table c-15 error bit (errf) value description 0 no error occurred 1 error occurred table c-16 receive fifo overrun bit (rfo) value description 0 no receiver buffer overrun occurred 1 receiver buffer overrun occurred table c-17 transmitter status field encoding (tms) value description 00 transmitter not involved 01 transmitter underrun 10 transmitter lost arbitration 11 transmitter successful table c-18 in-frame response bit (ifr) value description 0 not an ifr 1 ifr table c-19 in-frame response crc bit (ifrc) value description 0 ifr without crc 1 ifr with crc table c-20 error code field encoding value description 00 crc error 01 incomplete byte 10 bit timing error 11 break
MC68HC58 motorola technical data i-1 ? addr0 2-2 ? bitwise arbitration 3-9 block mode 4-20 break 3-4, 4-2, 4-3 assertion 4-21 break signal (break) 3-4 btad 5-4 buffers 1-1, 4-8 bus 2-2, 2-6, 2-7, 2-11 bus loading 2-12 receiver operation 4-16 transceiver 1-1 byte type and destination (btad) 5-4 ? case outline plcc b-3 soic b-4 cbr 5-1, 5-7 ccbr 5-12 central processing unit (cpu) 1-1 ceramic resonator 2-6, 2-11 circuits bus transceiver 1-1 control logic 1-1 class 2 1-1 clk 2-3, 4-4 clock internal frequency derivations 5-8 sources 2-12 types host interface 2-12 logic 2-12 cmos 1-1 command byte register (cbr) 5-1, c-1 bit fields byte type and destination (btad) 5-4 encoding summary 5-4 general command (gcom) 5-1 encoding summary 5-2 receive fifo command (rfc) 5-6 encoding summary 5-6 commands abort transmission 5-4 do not load 5-4 do nothing 5-2, 5-6 enter standby mode 5-2 flush byte 5-6 flush frame 5-6 load as configuration byte-immediate 2-17, 5-5 first and last byte of frame 5-6 first and last byte of transmit data 4-21 first byte of transmit data 5-5 last byte of transmit data 5-5 transmit data 5-4 load as configuration byte 5-5 send as last byte 4-20 break symbol 5-2 send ifr on eod with crc 5-2 send ifr on eod without crc 5-3 terminate auto retry 3-10, 5-3 completion code byte register (ccbr) 5-12, c-4 bits and bit fields error (errf) 5-12 error code (errc) 5-13 encoding summary 5-13 in-frame response (ifr) 5-13 in-frame response crc (ifrc) 5-13 receive fifo overrun (rfo) 5-12 transmitter status (tms) 5-12 encoding summary 5-12 configuration byte register (cbr) 5-7, c-2 bits and bit fields high speed control (4x) 5-8 interrupt mask (imsk) 5-7 interrupt mode (imod) 5-8 oscillator divisor (oscd) 5-8 test configuration (tc) 5-7 test mode control (tm) 5-7 control and status codes 5-1?-14 information types 5-1 logic 1-1 components 1-2 cpu 1-1 crc 3-3 cs 2-2, 2-7, 4-4, 4-8 cyclical redundancy check byte (crc) 3-3 index
motorola MC68HC58 i-2 technical data ? data 2-3 data link controller. see dlc 1-1 link idle (dli) 5-10 dlc electrical characteristics a-2 features 1-1 frame transmission 4-12 interrupt requests 4-11 operating conditions a-1 operation 4-1?-22 ordering information b-4 package dimensions b-3 parallel mode circuit diagram 2-5 data transfer 4-5 host mcu interface 4-5?-7 minimum time constraints 4-7 pin functions 2-2 servicing sequence 4-6 pin assignments 2-1, b-1 pins 6800 bus clock (clk) 2-3 address bit (addr0) 2-2 analog power ground (v ssa ) 2-4, 2-9 analog power supply voltage (v cc ) 2-4, 2-9 battery voltage (v batt ) 2-4, 2-9 chip-select (cs ) 2-2, 2-7 data bus (data) 2-3 digital power ground (v ssd ) 2-4, 2-9 digital power supply voltage (v dd ) 2-4, 2-9 external bias resistor (rext) 2-4, 2-8 external bus load (load) 2-3, 2-8 external oscillator (osc1/2) 2-3, 2-8 interrupt request (int ) 2-3, 2-8 logic in transceiver out (lito) 2-3, 2-8 logic out transceiver in (loti) 2-3, 2-8 parallel mode (prlmd) 2-3, 2-8 power supply enable (psen) 2-3, 2-8 read/write strobe (r/w ) 2-4 reset (rst ) 2-4, 2-8 sae j1850 multiplex bus (bus) 2-2, 2-7 serial clock (sclk) 2-9 slave in master out (simo) 2-9 slave out master in (somi) 2-9 serial mode byte format 4-8 circuit diagram 2-10 data transfer types 4-9 host mcu interface 4-8?-11 initialization routine 4-11 pin functions 2-7 receive routine 4-18 servicing sequence 4-9 spi exchange 4-9 transmit routine 4-14 dli 5-10 dominant bit 3-9 ? eclk 2-1 electrical characteristics a-1 end of data symbol (eod) 3-3 of frame symbol (eof) 3-4 eod 3-3 eof 3-4 errc 5-13 errf 5-12 error bit (errf) 5-12 code (errc) 5-13 external bias resistor 2-4, 2-6, 2-11 bus clock signal (eclk) 2-1 pull-up resistor 2-3, 2-8 ? fifo 1-1 first in, first out (fifo) 1-1 4x mode bit (4xmd) 5-11 4xmd 5-11 frame arbitration 3-9?-10 frames 1-1 composition 3-1 maximum length 3-2 sending 4-13 ? gcom 5-1 general command (gcom) 5-1 ? high speed transfer 4-3 host interface 4-3?-16 ? idle bus 3-5, 3-7 ifr 3-4, 4-21, 5-13 ifrc 4-22, 5-13 ifs 3-4 imod 5-8 imsk 5-7 inductor (l1) 2-6, 2-11 in-frame data bytes 3-2 response 4-21 bit (ifr) 5-13 bytes 3-4 crc bit (ifrc) 5-13 error conditions 4-22 int 2-3, 2-8, 2-14, 2-16, 4-4
MC68HC58 motorola technical data i-3 interface lines 4-4 inter-frame separation symbol (ifs) 3-4 interrupt requests (int ) 4-11 invalid active bit 3-7 passive bit 3-7 ? j1850 bus timing relationships 2-14, 2-15, 2-16 bus 3-2, 4-4 frame format 3-1 idle period 4-13 interface 1-1 message 3-1 protocol 1-1 transaction 1-1 frame format 3-1?-10 ? least significant bit (lsb) 3-2 lito 2-3, 2-8 load 2-3, 2-6, 2-8, 2-11 logic one 3-3 zero 3-3 logical wired-or arrangement 3-2 loti 2-3, 2-8 lsb 3-2 ? m6800 2-1 m68300 2-1, 2-7 m68hc05 2-7 m68hc11 2-1, 2-7 m68hc16 2-1, 2-7 mcu 1-1 mechanical data and ordering information b-1 how to obtain b-4 microcontroller data transfers 4-7 unit (mcu) 1-1 most significant bit (msb) 3-2 msb 3-2 ? nb 3-3, 4-22 netf 5-10 network fault (netf) 5-10 nodes 1-1, 2-12 noise 1-2, 2-6, 2-11 non -destructive contention protocol 3-2 -return to zero (nrz) 4-8 normal mode 4-2 normalization (nb) bit 3-3 /format (n/f) bit 4-22 nrz 4-8 null byte 4-4 ? operating modes 4-1 4x 4-2 block 4-3 normal 4-2 power off 4-2 reset 4-2 standby 4-2 opposite bit 3-10 ordering information b-4 osc1 2-3, 2-8, 2-12 osc2 2-3, 2-8, 2-12 oscd 5-8 ? parallel mode byte format 4-6 transfers 4-6 parameters parallel interface a-4 serial interface a-6 pin assignments 28-pin plcc b-1 28-pin soic b-2 plastic leaded chip carrier (plcc) 2-1 polynomial 3-3 power consumption 2-13 off mode 4-2 supply connections 2-13 method 1 2-14 method 2 2-15 method 3 2-16 prlmd 2-3, 2-8 psen 2-3, 2-8, 2-14, 2-15, 2-16 ? r/w 2-4, 4-4 receive fifo command (rfc) 5-6 fifo overrun (rf0) 5-12 fifo status (rfs) 5-9 first in/first out (rxfifo) 4-3 recessive bit 3-9 register bit field encodings c-1?-4 reset mode 4-2 resonators 2-12 rext 2-4
motorola MC68HC58 i-4 technical data rfc 5-6 rfo 5-12 rfs 5-9 rst 2-4, 2-8, 2-14, 2-15, 2-16 rxfifo 4-3, 4-12 ? sae 1-1 sclk 2-7, 2-9 polarity and phase 4-9 serial clock signal (sclk) 2-7 peripheral interface (spi) 2-7 signal and pin descriptions 2-1?-17 simo 2-9 slew rate 4-2 small outline integrated circuit (soic) 2-1, b-1 society of automotive engineers (sae) 1-1 sof 3-2, 4-21 soic 2-1, b-1 somi 2-9 spi 2-7 start of frame symbol (sof) 3-2 status byte contents 4-4 byte register (sbr) 5-8, c-3 bits and bit fields 4x mode (4xmd) 5-11 data link idle (dli) 5-10 network fault (netf) 5-10 receive fifo status (rfs) 5-9 encoding summary 5-9 txfifo status (tmfs) 5-11 encoding summary 5-11 information 5-1 symbols 3-1 active 3-2, 3-8 boundary differences 3-5 break (break) 3-4 end of data (eod) 3-3 end of frame (eof) 3-4 inter-frame separation (ifs) 3-4 passive 3-6 start of frame (sof) 3-2 ? tc 5-7 terminate auto retry 4-3, 4-13, 4-20 threshold windows 4-16 time constant 2-12 timing dlc interrupt a-7 parallel interface a-3 spi (active high sclk) a-5 spi (active low sclk) a-5 standby and interrupt a-8 tolerances 3-5 windows 4-12 tm 5-7 tmfs 5-11 tms 5-12 t nom 3-2 transceiver circuits 1-1 operation 1-2 transmit first in/first out (txfifo) 4-3 transmitter operation 4-12 status (tms) 5-12 txfifo 4-3, 4-12 status (tmfs) 5-11 ? valid active logic one 3-8 logic zero 3-8 sof symbol 3-9 variable pulse width (vpw) bit length 3-2 bitwise arbitration 3-9 modulation 3-2 symbols 3-5 valid/invalid bits and symbols 3-5?-9 v batt 1-2, 2-3, 2-4, 2-9, 2-15, 2-16 v cc 2-4, 2-9, 2-15, 2-16 v dd 2-4, 2-9, 2-16, 4-2 v ssa 2-4, 2-9 v ssd 2-4, 2-9 ? wakeup configuration 2-6, 2-11 waveshaping 1-2, 4-2 ? zener diodes 2-6, 2-11

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